參數(shù)資料
型號(hào): AD9517-4A/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 20/80頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9517-4A
設(shè)計(jì)資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-4 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9517-4A
主要屬性: 2 輸入,12 輸出,1.6GHz VCO
次要屬性: CMOS,LVPECL 和 LVDS 兼容
已供物品:
Data Sheet
AD9517-4
Rev. E | Page 27 of 80
DETAILED BLOCK DIAGRAM
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
AD9517-4
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_ SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NC
E
HOLD
OUT0
OUT1
OUT0
OUT1
LVPECL
DIVIDE BY
1 TO 32
OUT2
OUT3
OUT2
OUT3
LVPECL
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
DIVIDE BY
1 TO 32
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
T
0
64
28
-00
2
Figure 42. Detailed Block Diagram
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