參數(shù)資料
型號(hào): AD9517-4A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 65/80頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9517-4A
設(shè)計(jì)資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-4 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9517-4A
主要屬性: 2 輸入,12 輸出,1.6GHz VCO
次要屬性: CMOS,LVPECL 和 LVDS 兼容
已供物品:
AD9517-4
Data Sheet
Rev. E | Page 68 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x0AA
[5:3]
OUT7 ramp capacitors
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
4 (default)
0
1
3
0
1
0
3
0
1
2
1
0
3
1
0
1
2
1
0
2
1
[2:0]
OUT7 ramp current
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current Value (A)
0
200 (default)
0
1
400
0
1
0
600
0
1
800
1
0
1000
1
0
1
1200
1
0
1400
1
1600
0x0AB
[5:0]
OUT7 delay fraction
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000b gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Table 56. LVPECL Outputs
Reg.
Addr.
(Hex)
Bits
Name
Description
0x0F0
4
OUT0 invert
Sets the output polarity.
0: noninverting (default).
1: inverting.
[3:2]
OUT0 LVPECL
Sets the LVPECL output differential voltage (VOD).
differential voltage
3
2
VOD (mV)
0
400
0
1
600
1
0
780 (default)
1
960
[1:0]
OUT0 power-down
LVPECL power-down modes.
1
0
Mode
Output
0
Normal operation (default).
On
0
1
Partial power-down, reference on;
use only if there are no external load resistors.
Off
1
0
Partial power-down, reference on, safe LVPECL power-down.
Off
1
Total power-down, reference off;
use only if there are no external load resistors.
Off
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