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參數(shù)資料
| 型號(hào)： | AD9540BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR PLL 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 776 (CN2011-ZH PDF) |
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AD9540
Rev. A | Page 22 of 32
SERIAL PORT OPERATION
An AD9540 serial data port communication cycle has two
phases. Phase 1 is the instruction cycle, writing an instruction
byte to the AD9540, coincident with the first eight SCLK rising
edges. The instruction byte provides the AD9540 serial port
controller with information regarding the data transfer cycle,
which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines the serial address of the register being
accessed and whether the upcoming data transfer is read or
write.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9540. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9540
and the system controller.
The number of bytes transferred during Phase 2 of the commu-
nication cycle is a function of the register being accessed. For
example, when accessing Control Function Register 2, which is four
bytes wide, Phase 2 requires that four bytes be transferred. If
accessing a frequency tuning word, which is six bytes wide,
Phase 2 requires that six bytes be transferred. After transferring
all data bytes per the instruction, the communication cycle is
completed.
At the completion of any communication cycle, the AD9540
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9540 is registered on the rising edge of
SCLK. All data is driven out of the AD9540 on the falling edge
of SCLK. Figure 39 through Figure 42 are useful in understand-
ing the general operation of the AD9540 serial port.
.
04947-019
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 39. Serial Port Write Timing—Clock Stall Low
04947-020
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
D5
D4
D3
D2
D1
D0
D7
D6
SDO
CS
Figure 40. 3-Wire Serial Port Read Timing—Clock Stall Low
04947-021
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 41. Serial Port Write Timing—Clock Stall High
04947-022
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 42. 2-Wire Serial Port Read Timing—Clock Stall High
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| AD9540BCPZ-REEL | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNTHESIZER 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9540PCB | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9540 ,655 MHZ LOW JITTER CLOCK GEN - Trays |
| AD9540-VCO/PCBZ | 功能描述:BOARD EVAL CLK GEN SYNTH 48LFCSP RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081 |
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