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參數(shù)資料
| 型號： | AD9540BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR PLL 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9540
Rev. A | Page 28 of 32
CFR1[15] = 0 (default). Serial data transfer to the device is in
MSB first mode.
CFR1[15] = 1. Serial data transfer to the device is in LSB first mode.
CFR1[14] SDI/O Input Only (3-Wire Serial Data Mode)
The serial port on the AD9540 can act in 2-wire mode (SCLK
and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit
toggles the serial port between these two modes.
CFR1[14] = 0 (default). Serial data transfer to the device is in
2-wire mode. The SDI/O pin is bidirectional.
CFR1[14] = 1. Serial data transfer to the device is in 3-wire
mode. The SDI/O pin is input only.
CFR1[13:8] Open
Unused locations. Write a Logic 0.
CFR1[7] Digital Power-Down
This bit powers down the digital circuitry not directly related
to the I/O port. The I/O port functionality is not suspended,
regardless of the state of this bit.
CFR1[7] = 0 (default). Digital logic operating as normal.
CFR1[7] = 1. All digital logic not directly related to the I/O port
is powered down. Internal digital clocks are suspended.
CFR1[6] Phase Frequency Detector Input Power-Down
This bit controls the input buffers on the phase frequency
detector. It provides a way to gate external signals from the
phase frequency detector.
CFR1[6] = 0 (default). Phase frequency detector input buffers
are functioning normally.
CFR1[6] = 1. Phase frequency detector input buffers are
powered down, isolating the phase frequency detector from the
outside world.
CFR1[5] REFIN Crystal Enable
The AD9540 phase frequency detector has an on-chip oscillator
circuit. When enabled, the reference input to the phase fre-
quency detector (REFIN/REFIN) can be driven by a crystal.
CFR1[5] = 0 (default). The phase frequency detector reference
input operates as a standard analog input.
CFR1[5] = 1. The reference input oscillator circuit is enabled,
allowing the use of a crystal for the reference of the phase
frequency detector.
CFR1[4] SYNC_CLK Disable
If synchronization of multiple devices is not required, the
spectral energy resulting from this signal can be reduced by
gating the output buffer off. This function gates the internal
clock reference SYNC_CLK (SYSCLK ÷ 4) off of the
SYNC_OUT pin.
CFR1[4] = 0 (default). The SYNC_CLK signal is present on the
SYNC_OUT pin and is ready to be ported to other devices.
CFR1[4] = 1. The SYNC_CLK signal is gated off, putting the
SYNC_OUT pin into a high impedance state.
CFR1[3] Automatic Synchronization
One of the synchronization modes of the AD9540 forces the
DDS core to derive the internal reference from an external
reference supplied on the SYNC_IN pin. For details on
synchronization modes for the DDS core, see the
CFR1[3] = 0 (default). The automatic synchronization function
of the DDS core is disabled.
CFR1[3] = 1. The automatic synchronization function is on.
The device is slaved to an external reference and adjusts the
internal SYNC_CLK to match the external reference that is
supplied on the SYNC_IN input.
CFR1[2] Software Manual Synchronization
Rather than relying on the part to automatically synchronize the
internal clocks, the user can program the part to advance the
internal SYNC_CLK one system clock cycle. This bit is self
clearing and can be set multiple times.
CFR1[2] = 0 (default). The SYNC_CLK stays in the current
timing relationship to SYSCLK.
CFR1[2] = 1. The SYNC_CLK advances the rising and falling
edges by one SYSCLK cycle. This bit is then self-cleared.
CFR1[1] Hardware Manual Synchronization
Similar to the software manual synchronization (CFR1[2]), this
function enables the user to advance the SYNC_CLK rising edge by
one system clock period. This bit enables the SYNC_IN/STATUS
pin as a digital input. Once enabled, every rising edge on the
SYNC_IN input advances the SYNC_CLK by one SYSCLK period.
While enabled, the STATUS signal is not available on an external
pin. However, loop out-of-lock events trigger a flag in the Control
Register CFR1[24].
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| AD9540BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNTHESIZER 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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