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參數(shù)資料
| 型號： | AD9540BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/32頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR PLL 48-LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9540
Rev. A | Page 30 of 32
CFR2[24] = 0 (default). The lock detect acts as a status indicator
(PLL is locked 0 or unlocked 1).
CFR2[24] = 1. The lock detect acts as a lead-lag indicator. A 1
on the STATUS pin means that the CLK2 pin lags the
reference. A 0 means that the CLK2 pin leads the reference.
CFR2[23] RF Divider Power-Down
This bit powers down the RF divider to save power when
not in use.
CFR2[23] = 0 (default). The RF divider is on.
CFR2[23] = 1. The RF divider is powered down and an alternate
path between the CLK1 inputs and SYSCLK is enabled.
CFR2[22:21] RF Divider Ratio
These two bits control the RF divider ratio (÷R).
CFR2[22:21] = 11 (default). RF Divider R = 8.
CFR2[22:21] = 10. RF Divider R = 4.
CFR2[22:21] = 01. RF Divider R = 2.
CFR2[22:21] = 00. RF Divider R = 1. Note that this is not the
same as bypassing the RF divider.
CFR2[20] Clock Driver Power-Down
This bit powers down the CML clock driver circuit.
CFR2[20] =1 (default). The CML clock driver circuit is
powered down.
CFR2[20] = 0. The CML clock driver is powered up.
CFR2[19:18] Clock Driver Input Select
These bits control the mux on the input for the CML clock
driver.
CFR2[19:18] = 00. The CML clock driver is disconnected from
all inputs (and does not toggle).
CFR2[19:18] = 01. The CML clock driver is driven by the CLK2
input pin.
CFR2[19:18] = 10 (default). The CML clock driver is driven by
the output of the RF divider.
CFR2[19:18] = 11. The CML clock driver is driven by the input
of the RF divider
CFR2[17] Slew Rate Control Bit
Even without the additional surge current supplied by the rising
edge slew rate control bits and the falling edge slew rate control
bits, the device applies a default 7.6 mA surge current to the
rising edge and a 4.05 mA surge current to the falling edge.
This bit disables all slew rate enhancement surge current,
including the default values.
CFR2[17] = 0 (default). The CML driver applies default surge
current to rising and falling edges.
CFR2[17] = 1. Driver applies no surge current during
transitions. The only current is the continuous current.
CFR2[16] RF Divider CLK1 Mux
This bit toggles the mux to control whether the RF divider
output or input is supplying SYSCLK to the device.
CFR2[16] = 0 (default). The RF divider output supplies the
DDS SYSCLK.
CFR2[16] = 1. The RF divider input supplies the DDS SYSCLK
(bypass the divider). Note that regardless of the condition of the
configuration of the clock input, the DDS SYSCLK must not
exceed the maximum rated clock speed.
CFR2[15:12] CLK2 Divider (÷N) Control Bits
These four bits set the CLK2 divider (÷N) ratio where N is a
value = 1 to 16, and CFR2[15:12] = 0000 means that N = 1 and
CFR2[15:12] = 1111 means that N = 16 or simply, N =
CFR2[15:12] + 1.
Table 7. CLK2 Divider Values (÷N)
CFR2[15:12]
N
CFR2[15:12]
N
0000
1
1000
9
0001
2
1001
10
0010
3
1010
11
0011
4
1011
12
0100
5
1100
13
0101
6
1101
14
0110
7
1110
15
0111
8
1111
16
CFR2[11:8] REFIN Divider (÷M) Control Bits
These 4 bits set the REFIN divider (÷M) ratio where the M = 1
to 16 and CFR2[11:8] = 0000 means that M = 1, and
CFR2[11:8] = 1111 means that M = 16 or M = CFR2[11:8] + 1.
Table 8. REFIN Input Divider Values (÷M)
CFR2[15:12]
M
CFR2[11:8]
M
0000
1
1000
9
0001
2
1001
10
0010
3
1010
11
0011
4
1011
12
0100
5
1100
13
0101
6
1101
14
0110
7
1110
15
0111
8
1111
16
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