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參數(shù)資料
| 型號： | AD9540BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR PLL 48-LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 655MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9540
Rev. A | Page 31 of 32
CFR2[7:6] Open
Unused locations. Write a Logic 0.
CFR2[5] CP Polarity
This bit sets the polarity of the charge pump in response to a
ground referenced or a supply referenced VCO.
CFR2[5] = 0 (default). The charge pump is configured to
operate with a supply referenced VCO. If CLK2 lags REFIN, the
charge pump attempts to drive the VCO control node voltage
higher. If CLK2 leads REFIN, the charge pump attempts to
drive the VCO control node voltage lower.
CFR2[5] = 1. The charge pump is configured to operate with a
ground referenced VCO. If CLK2 lags REFIN, the charge pump
attempts to drive the VCO control node voltage lower. If CLK2
leads REFIN, the charge pump attempts to drive the VCO
control node voltage higher.
CFR2[4] Charge Pump Full Power-Down
This bit, when set, puts the charge pump into a full power-down
mode.
CFR2[4] = 0 (default). The charge pump is powered on and
operating normally.
CFR2[4] = 1. The charge pump is powered down completely.
CFR2[3] Charge Pump Quick Power-Down
Rather than power down the charge pump, which have a long
recovery time, a quick power-down mode that powers down
only the charge pump output buffer is included. Though this
does not reduce the power consumption significantly, it does
shut off the output to the charge pump and allows it to come
back on rapidly.
CFR2[3] = 0 (default). The charge pump is powered on and
operating normally.
CFR2[3] = 1. The charge pump is on and running, but the
output buffer is powered down.
CFR2[2:0] Charge Pump Current Scale
A base output current from the charge pump is determined by a
resistor connected from the CP_RSET pin to ground (see the
PLL Circuitry section). However, it is possible to multiply the
charge pump output current by a value from 1:8 by program-
ming these bits. The charge pump output current is scaled by
CFR2[2:0] +1.
CFR2[2:0] = 000 (default)
Scale factor = 1 to CFR2[2:0] = 111 (8).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9540BCPZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNTHESIZER 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9540PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:655 MHz Low Jitter Clock Generator |
| AD9540-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9540 ,655 MHZ LOW JITTER CLOCK GEN - Trays |
| AD9540-VCO/PCBZ | 功能描述:BOARD EVAL CLK GEN SYNTH 48LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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