參數(shù)資料
型號(hào)： AD9540BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GENERATOR PLL 48-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器
PLL： 是
輸入： 時(shí)鐘
輸出： CML，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 655MHz
除法器/乘法器： 是/無(wú)
電源電壓： 1.71 V ~ 1.89 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9540
Rev. A | Page 29 of 32
CFR1[1] = 0 (default). The hardware manual synchronization
function is disabled. Either the part is outputting the STATUS
(CFR1[3] = 0) or it is using the SYNC_IN to slave the
SYNC_CLK signal to an external reference provided on
SYNC_IN (CFR1[3] = 1).
CFR1[1] = 1. The SYNC_IN/STATUS pin is set as a digital
input. Each subsequent rising edge on this pin advances the
SYNC_CLK rising edge by one SYSCLK period.
CFR1[0] High Speed Synchronization Enable Bit
This bit enables extra functionality in the autosynchronization
algorithm, which enables the device to synchronize high speed
clocks (SYNC_CLK > 62.5 MHz).
CFR1[0] = 0 (default). High speed synchronization is disabled.
CFR1[0] = 1. High speed synchronization is enabled.
Control Function Register 2 (CFR2)
The Control Register 2 is comprised of five bytes, that must be
written during a write operation involving CFR2. With some
minor exceptions, the CFR2 primarily controls analog and
timing functions on the AD9540.
CFR2[39] DAC Power-Down Bit
This bit powers down the DAC portion of the AD9540 and puts
it into the lowest power dissipation state.
CFR2[39] = 0 (default). DAC is powered on and operating.
CFR2[39] = 1. DAC is powered down and the output is in a
high impedance state.
CFR2[38:34] Open
Unused locations. Write a Logic 0.
CFR2[33] Internal Band Gap Power-Down
To shut off all internal quiescent current, the band gap needs to
be powered down. This is normally not done because it takes a
long time (~10 ms) for the band gap to power up and settle to
its final value.
CFR2[33] = 0. Even when all other sections are powered down,
the band gap is powered up and is providing a regulated voltage.
CFR2[33] = 1. The band gap is powered down.
CFR2[32] Internal CML Driver DRV_RSET
To program the CML driver output current, a resistor must
be placed between the DRV_RSET pin and ground. This bit
enables an internal resistor to program the output current
of the driver.
CFR2[32] = 0 (default). The DRV_RSET pin is enabled, and an
external resistor must be attached to the CP_RSET pin to
program the output current.
CFR2[32] = 1. The CML current is programmed by the internal
resistor and ignores the resistor on the DRV_RSET pin.
CFR2[31:29] Clock Driver Rising Edge
These bits control the slew rate of the rising edge of the CML
clock driver output. When these bits are on, additional current
is sent to the output driver to increase the rising edge slew rate
capability. Table 5 describes how the bits increase the current.
The additional current is on only during the rising edge of the
waveform for approximately 250 ps, not during the entire
transition.
Table 5. CML Clock Driver Rising Edge Slew Rate Control
Bits and Associated Surge Current
CFR2[31] = 1
7.6 mA
CFR2[30] = 1
3.8 mA
CFR2[29] = 1
1.9 mA
CFR2[28:26] Clock Driver Falling Edge Control
These bits control the slew rate of the falling edge of the CML
clock driver output. When these bits are on, additional current
is sent to the output driver to increase the rising edge slew rate
capability. Table 6 describes how the bits increase the current.
The additional current is on only during the rising edge of the
waveform, for approximately 250 ps, not during the entire
transition.
Table 6. CML Clock Drive Falling Edge Slew Rate Control
Bits and Associated Surge Current
CFR2[28] = 1
5.4 mA
CFR2[30] = 1
2.7 mA
CFR2[29] = 1
1.35 mA
CFR2[25] PLL Lock Detect Enable
This bit enables the SYNC_IN/STATUS pin as a lock detect
output for the PLL.
CFR2[25] = 0 (default).The STATUS_DETECT signal is
disabled.
CFR2[25] = 1. The STATUS_DETECT signal is enabled.
CFR2[24] PLL Lock Detect Mode
This bit toggles the modes of the PLL lock detect function. The
lock detect can either be a status indicator (locked or unlocked)
or it can indicate a lead-lag relationship between the two phase
frequency detector inputs.
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