參數(shù)資料
型號: AD9640ABCPZ-80
廠商: Analog Devices Inc
文件頁數(shù): 10/52頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS 64LFCSP
設計資源: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
標準包裝: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 492mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
AD9640
Rev. B | Page 18 of 52
Pin No.
Mnemonic
Type
Function
Digital Inputs
52
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
63
D0+ (LSB)
Output
Channel A/Channel B LVDS Output Data 0—True.
62
D0 (LSB)
Output
Channel A/Channel B LVDS Output Data 0—Complement.
3
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
2
D1
Output
Channel A/Channel B LVDS Output Data 1—Complement.
5
D2+
Output
Channel A/Channel B LVDS Output Data 2—True.
4
D2
Output
Channel A/Channel B LVDS Output Data 2—Complement.
7
D3+
Output
Channel A/Channel B LVDS Output Data 3—True.
6
D3
Output
Channel A/Channel B LVDS Output Data 3—Complement.
9
D4+
Output
Channel A/Channel B LVDS Output Data 4—True.
8
D4
Output
Channel A/Channel B LVDS Output Data 4—Complement.
13
D5+
Output
Channel A/Channel B LVDS Output Data 5—True.
12
D5
Output
Channel A/Channel B LVDS Output Data 5—Complement.
15
D6+
Output
Channel A/Channel B LVDS Output Data 6 —True.
14
D6
Output
Channel A/Channel B LVDS Output Data 6—Complement.
17
D7+
Output
Channel A/Channel B LVDS Output Data 7—True.
16
D7
Output
Channel A/Channel B LVDS Output Data 7—Complement.
19
D8+
Output
Channel A/Channel B LVDS Output Data 8—True.
18
D8
Output
Channel A/Channel B LVDS Output Data 8—Complement.
23
D9+
Output
Channel A/Channel B LVDS Output Data 9—True.
22
D9
Output
Channel A/Channel B LVDS Output Data 9—Complement.
26
D10+
Output
Channel A/Channel B LVDS Output Data 10—True.
25
D10
Output
Channel A/Channel B LVDS Output Data 10—Complement.
28
D11+
Output
Channel A/Channel B LVDS Output Data 11—True.
27
D11
Output
Channel A/Channel B LVDS Output Data 11—Complement.
30
D12+
Output
Channel A/Channel B LVDS Output Data 12—True.
29
D12
Output
Channel A/Channel B LVDS Output Data 12—Complement.
32
D13+ (MSB)
Output
Channel A/Channel B LVDS Output Data 13—True.
31
D13 (MSB)
Output
Channel A/Channel B LVDS Output Data 13—Complement.
11
DCO+
Output
Channel A/Channel B LVDS Data Clock Output—True.
10
DCO
Output
Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
48
SCLK/DFS
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
47
SDIO/DCS
Input/Output
SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode.
51
CSB
Input
SPI Chip Select (Active Low).
Signal Monitor Ports
33
SMI SDO/OEB
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
35
SMI SDFS
Output
Signal Monitor Serial Data Frame Sync.
34
SMI SCLK/PDWN
Input/Output
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
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