參數(shù)資料
型號： AD9640ABCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 32/52頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS 64LFCSP
設(shè)計資源： Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 492mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
AD9640
Rev. B | Page 38 of 52
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9640 includes built-in test features to enable verification
of the integrity of each channel as well as to facilitate board level
debugging. A built-in self-test (BIST) feature is included that
verifies the integrity of the digital data path of the AD9640.
Various output test options are also provided to place predictable
values on the outputs of the AD9640.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9640 signal path. When enabled, the test runs from an internal
PN source through the digital data path starting at the ADC
block output. The BIST sequence runs for 512 cycles and stops.
The BIST signature value for Channel A or Channel B is placed
in Register 0x024 and Register 0x025. If one channel is chosen,
its BIST signature is written to the two registers. If both channels
are chosen, the results from the A channel are placed in the
BIST signature register.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or started from the beginning,
based on the value programmed in Register 0x00E, Bit 2. The
BIST signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 25. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital backend blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
相關(guān)PDF資料
PDF描述
ADM5170AP-REEL IC TXRX RS232/423 OCTAL 28PLCC
MS27508E12A98S CONN RCPT 10POS BOX MNT W/SCKT
GTC06AF-16-11P CONN PLUG 2POS STRAIGHT W/PINS
MS27508E22B55PA CONN RCPT 55POS BOX MNT W/PINS
MS27467E9A35S CONN PLUG 6POS STRAIGHT W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9640ABCPZRL7-105 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14Bit 105Msps Dual 1.8V PB Free ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9640ABCPZRL7-125 功能描述:14 Bit Analog to Digital Converter 2 Input 2 Pipelined 64-LFCSP-VQ (9x9) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 位數(shù):14 采樣率（每秒）:125M 輸入數(shù):2 輸入類型:差分，單端 數(shù)據(jù)接口:并聯(lián) 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):2 架構(gòu):管線 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:1.7 V ~ 1.9 V 電壓 - 電源，數(shù)字:1.7 V ~ 1.9 V 特性:同步采樣 工作溫度:-40°C ~ 85°C 封裝/外殼:64-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:64-LFCSP-VQ（9x9） 標(biāo)準(zhǔn)包裝:750
AD9640ABCPZRL7-80 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9640BCPZ-105 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 14-bit Parallel 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC ADC 14BIT 105MSPS LFCSP-64
AD9640BCPZ-125 制造商:Analog Devices 功能描述:IC ADC 14BIT 125MSPS LFCSP-64 制造商:Analog Devices 功能描述:IC, ADC, 14BIT, 125MSPS, LFCSP-64, Resolution (Bits):14bit, Sampling Rate:150MSP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*