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參數(shù)資料
| 型號(hào)： | AD9736-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 25/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9736 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 設(shè)計(jì)資源： | AD9736-DPG2-EBZ Schematic AD9736-DPG2-EBZ BOM AD9736-DPG2-EBZ Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1.2G |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9736 |
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AD9734/AD9735/AD9736
Rev. A | Page 31 of 72
FULL SCALE CURRENT (FSC) REGISTERS (REG. 2, REG. 3)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x02
FSC_1
SLEEP
–
FSC<9>
FSC<8>
0x03
FSC_2
FSC<7>
FSC<6>
FSC<5>
FSC<4>
FSC<3>
FSC<2>
FSC<1>
FSC<0>
Table 12. Full Scale Current Output Register Bit Descriptions
Bit Name
Read/Write
Description
SLEEP
WRITE
0, enable DAC output.
1, set DAC output current to 0 mA.
FSC<9:0>
WRITE
0x000, 10 mA full-scale output current.
0x200, 20 mA full-scale output current.
0x3FF, 30 mA full-scale output current.
LVDS CONTROLLER (LVDS_CNT) REGISTERS (REG. 4, REG. 5, REG. 6)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x04
LVDS_CNT1
MSD<3>
MSD<2>
MSD<1>
MSD<0>
MHD<3>
MHD<2>
MHD<1>
MHD<0>
0x05
LVDS_CNT2
SD<3>
SD<2>
SD<1>
SD<0>
LCHANGE
ERR_HI
ERR_LO
CHECK
0x06
LVDS_CNT3
LSURV
LAUTO
LFLT<3>
LFLT<2>
LFLT<1>
LFLT<0>
LTRH<1>
LTRH<0>
Table 13. LVDS Controller Register Bit Descriptions
Bit Name
Read/Write
Description
MSD<3:0>
WRITE
0x0, set setup delay for the measurement system.
READ
If ( LAUTO = 1), the latest measured value for the setup delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
MHD<3:0>
WRITE
0x0, set hold delay for the measurement system.
READ
If ( LAUTO = 1), the latest measured value for the hold delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
SD<3:0>
WRITE
0x0, set sample delay.
READ
If ( LAUTO = 1), the result of a measurement cycle is stored in this register.
If ( LAUTO = 0), readback of the last SPI write to this bit.
LCHANGE
READ
0, no change from previous measurement.
1, change in value from the previous measurement.
NOTE: The average filter and the threshold detection are not applied to this bit.
ERR_HI
READ
One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduced link specification.
ERR_LO
READ
One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link specification.
CHECK
READ
0, phase measurement—sampling in the previous or following DATA cycle.
1, phase measurement—sampling in the correct DATA cycle.
LSURV
WRITE
0, the controller stops after completion of the current measurement cycle.
1, continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the
threshold value.
LAUTO
WRITE
0, sample delay is not automatically updated.
1, continuously starts measurement cycles and updates the sample delay according to the measurement.
NOTE: LSURV (Reg. 6, Bit 7) must be set to 1 and the LVDS IRQ (Reg. 1, Bit 3) must be set to 0 for AUTO mode.
LFLT<3:0>
WRITE
0x0, average filter length, Delay = Delay + Delta Delay/2^ LFLT <3:0>, values greater than 12 (0x0C) are
clipped to 12.
LTRH<2:0>
WRITE
000, set auto update threshold values.
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| AD9737ABBCZ | 功能描述:IC DAC 11BIT 2.5GSPS RF 160BGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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