參數(shù)資料
型號(hào): AD9736-DPG2-EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 28/72頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9736
產(chǎn)品培訓(xùn)模塊: DAC Architectures
設(shè)計(jì)資源: AD9736-DPG2-EBZ Schematic
AD9736-DPG2-EBZ BOM
AD9736-DPG2-EBZ Gerber Files
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 1.2G
數(shù)據(jù)接口: 并聯(lián)
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9736
AD9734/AD9735/AD9736
Rev. A | Page 34 of 72
CONTROLLER CLOCK PREDIVIDER (CCLK_DIV) READING REGISTER (REG. 22)
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x16
CCLK_DIV
RESERVED
CCD<3>
CCD<2>
CCD<1>
CCD<0>
Table 18. Controller Clock Predivider Register Bit Descriptions
Bit Name
Read/Write
Description
CCD<3:0>
WRITE
0x0, controller clock = DACCLK/16.
0x1, controller clock = DACCLK/32.
0x2, controller clock = DACCLK/64 …
0xF, controller clock = DACCLK/524288.
NOTE: The 100 MHz to 1.2 GHz DACCLK must be divided to less than 10 MHz for correct operation. CCD<3:0>
must be programmed to divide the DACCLK so that this relationship is not violated. Controller clock =
DACCLK/(2 ^ ( CCD<3:0> + 4 )).
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