參數(shù)資料
型號(hào)： AD9739A-FMC-EBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 23/64頁(yè)
文件大小： 0K
描述： BOARD EVAL W/FMC CONN FPGA DEV
設(shè)計(jì)資源： AD9739A-FMC-EBZ Gerber Files
AD9739A-FMC-EBZ Layout
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 2.5G
數(shù)據(jù)接口： 串行，SPI?
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9739A
Data Sheet
AD9737A/AD9739A
Rev. C | Page 3 of 64
REVISION HISTORY
2/12—Rev. B to Rev. C
Changes to Figure 5...........................................................................9
Changes to Table 7 ..........................................................................11
Changes to Ordering Guide...........................................................63
2/12—Rev. A to Rev. B
Added AD9737A ................................................................ Universal
Reorganized Layout ........................................................... Universal
Moved Revision History Section.....................................................3
Deleted ±6% from Table Summary Statement; Changes
to Table 1 ............................................................................................4
Deleted ±6% from Table Summary Statement, Table 2................5
Deleted ±6% from Table Summary Statement, Table 3................6
Changes to AC Specifications Section and Table 4.......................7
Added Figure 5, Renumbered Sequentially ...................................9
Added Figure 7 and Table 7, Renumbered Sequentially ............10
Deleted Figure 24 ............................................................................13
Added Typical Performance Characteristics—AD9737A
Section and Figure 9 to Figure 77 .................................................14
Deleted Table 9 ................................................................................25
Added Static Linearity Section and Figure 78 to Figure 88 ............26
Added Figure 106 ............................................................................30
Changes to Figure 116, Figure 117, Figure 118, Figure 119,
Figure 120, and Figure 121.............................................................33
Changes to Figure 122, Figure 123, Figure 124, Figure 125,
Figure 126, and Figure 127.............................................................34
Changes to Figure 128, Figure 129, Figure 130, Figure 131,
Figure 132, and Figure 133.............................................................35
Changes to Figure 134, Figure 135, Figure 136, Figure 137,
Figure 138, and Figure 139.............................................................36
Changes to Figure 140, Figure 141, Figure 142, Figure 143,
Figure 144, and Figure 145.............................................................37
Changes to Figure 146, Figure 147, Figure 148, Figure 149,
and Figure 150; Added Figure 151 ................................................38
Added Table 10 ................................................................................42
Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC Section, Controller
Clock Disable Section, and Table 11 to Table 13 ........................43
Added Interrupt Request (IRQ) Enable/Status Section, TxDAC
Full-Scale Current Setting (IOUTFS) and Sleep Section, TxDAC
Quad-Switch Mode of Operation Section, DCI Phase
Alignment Status Section, Data Receiver Controller
Configuration Section, and Table 14 to Table 18........................44
Added Data Receiver Controller_Data Sample Delay Value
Section, Data Receiver Controller_DCI Delay Value/Window
and Phase Rotation Section, Data Receiver Controller_Delay
Line Status Section, Data Receiver Controller Lock/Tracking
Status Section, and Table 19 to Table 22 ......................................45
Added CLK Input Common Mode Section, and Mu
Controller Configuration and Status Section, and Table 23
and Table 24 .....................................................................................46
Added Part ID Section, and Table 25 ...........................................47
Changes to LVDS Data Port Interface Section............................49
Changes to Data Receiver Controller Initialization
Description Section ........................................................................51
Changes to Mu Controller Section ...............................................52
Added Figure 167 and Table 27, Changes to Mu Controller
Initialization Description Section.................................................53
Changes to Analog Modes of Operation Section, Figure 171,
and Figure 172 .................................................................................55
Updated Outline Dimensions........................................................63
Changes to Ordering Guide...........................................................63
7/11—Rev. 0 to Rev. A
Changed Maximum Update Rate (DACCLK Input) Parameter
to DAC Clock Rate Parameter in Table 4.......................................6
Added Adjusted DAC Update Rate Parameter and Endnote 1 in
Table 4.................................................................................................6
Updated Outline Dimensions........................................................43
1/11—Revision 0: Initial Version
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