參數(shù)資料
型號: AD9739A-FMC-EBZ
廠商: Analog Devices Inc
文件頁數(shù): 64/64頁
文件大?。?/td> 0K
描述: BOARD EVAL W/FMC CONN FPGA DEV
設(shè)計資源: AD9739A-FMC-EBZ Gerber Files
AD9739A-FMC-EBZ Layout
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC®
DAC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 2.5G
數(shù)據(jù)接口: 串行,SPI?
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9739A
Data Sheet
AD9737A/AD9739A
Rev. C | Page 9 of 64
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
09616-
002
AD9737A/AD9739A
14
13
12
11
10
8
7
6
3
2
19
5
4
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VSSA, ANALOG SUPPLY GROUND
VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD
VDDA, 3.3V, ANALOG SUPPLY
Figure 2. Analog Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
13
12
11
10
8
7
6
3
2
19
5
4
VSS DIGITAL SUPPLY GROUND
VDD33, 3.3V DIGITAL SUPPLY
VDD, 1.8V, DIGITAL SUPPLY
0961
6-
003
AD9737A/AD9739A
Figure 3. Digital Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
13
12
11
10
8
7
6
3
2
19
5
4
VSSC, CLOCK SUPPLY GROUND
VDDC, 1.8V, CLOCK SUPPLY
09616-
004
AD9737A/AD9739A
Figure 4. Digital LVDS Clock Supply Pins (Top View)
A
B
E
F
G
H
J
K
L
DB1[0:10]P
M
DB1[0:10]N
C
DACCLK_N
D
DACCLK_P
DB0[0:10]P
N
DB0[0:10]N
P
14
13
12
11
10
8
7
6
3
2
19
5
4
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
DCI_P/_N
DCO_P/_N
09
616
-03
6
AD9737A
Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
DB1[0:13]P
DB1[0:13]N
DB0[0:13]P
DB0[0:13]N
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
DACCLK_N
DACCLK_P
N
P
14
13
12
11
10
8
7
6
3
2
19
5
4
DCI_P/_N
DCO_P/_N
09
61
6-
00
5
AD9739A
Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View)
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