參數(shù)資料
型號： AD9739A-FMC-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 39/64頁
文件大?。?/td> 0K
描述： BOARD EVAL W/FMC CONN FPGA DEV
設(shè)計資源： AD9739A-FMC-EBZ Gerber Files
AD9739A-FMC-EBZ Layout
標準包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 2.5G
數(shù)據(jù)接口： 串行，SPI?
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9739A
AD9737A/AD9739A
Data Sheet
Rev. | Page 44 of 64
INTERRUPT REQUEST (IRQ) ENABLE/STATUS
Table 14. Interrupt Request (IRQ) Enable (IRQ_EN)/Status (IRQ_REQ) Register
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x03
MU_LST_EN
3
W
0x0
This register enables the Mu and LVDS Rx controllers to update their
corresponding IRQ status bits in Register 0x04, which defines whether the
controller is locked (LCK) or unlocked (LST).
0 = disable (resets the status bit), 1 = enable.
MU_LCK_EN
2
W
0x0
RCV_LST_EN
1
W
0x0
RCV_LCK_EN
0
W
0x0
0x04
MU_LST_IRQ
3
R
0x0
This register indicates the status of the controllers.
For LCK_IRQ bits: 0 = lock lost, 1 = locked.
For LST_IRQ bits: 0 = lock not lost, 1 = unlocked.
Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03
should be reset by writing 0, followed by another write of 1 to enable.
MU_LCK_IRQ
2
R
0x0
RCV_LST_IRQ
1
R
0x0
RCV_LCK_IRQ
0
R
0x0
TxDAC FULL-SCALE CURRENT SETTING (IOUTFS) AND SLEEP
Table 15. TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Register (FSC_1 and FSC_2)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x06
FSC[7:0]
[7:0]
R/W
0x00
Sets the TxDAC IOUTFS current between 8 mA and 31 mA (default = 20 mA).
IOUTFS = 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023.
0x07
FSC[9:8]
[1:0]
R/W
0x02
Sleep
7
R/W
0 = enable DAC output, 1 = disable DAC output (sleep).
TxDAC QUAD-SWITCH MODE OF OPERATION
Table 16. TxDAC Quad-Switch Mode of Operation Register (DEC_CNT)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x08
DAC_DEC
[1:0]
R/W
0x00
0x00 = normal baseband mode.
0x02 = mix-mode.
DCI PHASE ALIGNMENT STATUS
Table 17. DCI Phase Alignment Status Register (LVDS_STAT1)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x0C
DCI_PRE_PH0
2
R
0x0
0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling
edge.
1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling
edge.
DCI_PST_PH0
0
R
0x0
0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling
edge.
1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling
edge.
DATA RECEIVER CONTROLLER CONFIGURATION
Table 18. Data Receiver Controller Configuration Register (LVDS_REC_CNT1)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x10
RCVR_FLG_RST
2
W
0x0
Data receiver controller flag reset. Write 1 followed by 0 to reset flags.
RCVR_LOOP_ON
1
R/W
0x1
0 = disable, 1 = enable.
When this bit is enabled, the data receiver controller generates an IRQ; it
falls out of lock and automatically begins a search/track routine.
RCVR_CNT_ENA
0
R/W
0x0
Data receiver controller enable. 0 = disable, 1 = enable.
C
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