- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8579 > AD9776BSVZRL (Analog Devices Inc)IC DAC 12BIT DUAL 1GSPS 100TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9776BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 22/56頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL 1GSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 1G |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)
AD9776/AD9778/AD9779
Rev. A | Page 29 of 56
Address
Register Name
Reg. No.
Bits
Description
Function
Default
Sync Control Register
06
7:4
Sync input delay
See the Multiple DAC Synchronization
section for details on using these registers
to synchronize multiple DACs
0
06
3:0
Input sync pulse timing error
tolerance
0
07
7
Sync receiver enable
0
07
6
Sync driver enable
0
07
5
Sync triggering edge
0
07
4:0
SYNC_I to input data sampling
clock offset
0
PLL Control
08
7:2
PLL band select
VCO frequency range vs. PLL band select
value (see Table 18)
111001
08
1:0
VCO AGC gain control
Lower number (low gain) is generally better
for performance
11
09
7
PLL enable
0: PLL off, DAC rate clock supplied by
outside source
0
1: PLL on, DAC rate clock synthesized
internally from external reference clock via
PLL clock multiplier
09
6:5
PLL VCO divide ratio
FVCO/fDAC
00 × 1
01 × 2
10 × 4
11 × 8
09
4:3
PLL loop divide ratio
fDAC/fREF
00 × 2
01 × 4
10 × 8
11 × 16
09
2:0
PLL bias setting
Always set to 010
010
0A
7:5
PLL control voltage range
000 to 111, proportional to voltage at PLL
loop filter output, readback only
Misc Control
0A
4:0
PLL loop bandwidth adjustment
See PLL Loop Filter Bandwidth section for
details
I DAC Control Register
0B
7:0
I DAC gain adjustment
(7:0) LSB slice of 10-bit gain setting word
for I DAC
11111001
0C
7
I DAC sleep
0: I DAC on
0
1: I DAC off
0C
6
I DAC power-down
0: I DAC on
0
1: I DAC off
0C
1:0
I DAC gain adjustment
(9:8) MSB slice of 10-bit gain setting word
for I DAC
01
0D
7:0
Aux DAC1 gain adjustment
(7:0) LSB slice of 10-bit gain setting word for
Aux DAC1
00000000
0E
7
Aux DAC1 sign
0: positive
1: negative
0E
6
Aux DAC1 current direction
0: source
0
1: sink
0E
5
Aux DAC1 power-down
0: Aux DAC1 on
0
1: Aux DAC1 off
Aux DAC1 Control
Register
0E
1:0
Aux DAC1 gain adjustment
(9:8) MSB slice of 10-bit gain setting word
for Aux DAC1
00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NCS2553DR2G | IC TRPL VIDEO AMP W/FILTER 8SOIC |
| VE-261-MY-B1 | CONVERTER MOD DC/DC 12V 50W |
| VE-260-MY-B1 | CONVERTER MOD DC/DC 5V 50W |
| AD5391BCPZ-5-REEL7 | IC DAC 12BIT 16CHAN 5V 64LFCSP |
| AD5391BCPZ-5-REEL | IC DAC 12BIT 16CHAN 5V 64-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9776-EB | 制造商:Analog Devices 功能描述:AD9776 EVAL BOARD - Bulk |
| AD9776-EBZ | 制造商:Analog Devices 功能描述:DUAL 12B, 1.0 GSPS TXDAC - Bulk |
| AD9777 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| AD9777BSV | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 16-bit 80-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:16BIT 160 MSPS DUAL TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty |
| AD9777BSVRL | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 16-bit 80-Pin TQFP EP T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。