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參數(shù)資料
| 型號(hào)： | AD9776BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL 1GSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9776/AD9778/AD9779
Rev. A | Page 37 of 56
Table 18. VCO Frequency Range vs. PLL Band Select Value
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Typ at 25°C
Typ over Temp
PLL Band Select
fLOW
fHIGH
fLOW
fHIGH
111111 (63)
Auto mode
111110 (62)
2056
2170
2105
2138
111101 (61)
2002
2113
2048
2081
111100 (60)
1982
2093
2029
2061
111011 (59)
1964
2075
2010
2043
111010 58)
1947
2057
1992
2026
111001 (57)
1927
2037
1971
2006
111000 (56)
1907
2016
1951
1986
110111 (55)
1894
2003
1936
1972
110110 (54)
1872
1981
1913
1952
110101 (53)
1852
1960
1892
1931
110100 (52)
1841
1948
1881
1920
110011 (51)
1816
1923
1855
1895
110010 (50)
1796
1903
1835
1874
110001 (49)
1789
1895
1828
1867
110000 (48)
1764
1871
1803
1844
101111 (47)
1746
1853
1784
1826
101110 (46)
1738
1842
1776
1815
101101 (45)
1714
1820
1752
1794
101100 (44)
1700
1804
1737
1779
101011 (43)
1689
1790
1726
1764
101010 (42)
1657
1757
1695
1734
101001 (41)
1641
1738
1679
1714
101000 (40)
1610
1707
1649
1684
100111 (39)
1597
1689
1635
1666
100110 (38)
1568
1661
1607
1639
100101 (37)
1553
1641
1592
1617
100100 (36)
1525
1613
1562
1592
100011 (35)
1511
1595
1548
1572
100010 (34)
1484
1570
1519
1549
100001 (33)
1470
1552
1506
1528
100000 (32)
1441
1525
1474
1504
011111 (31)
1429
1509
1463
1487
011110 (30)
1403
1485
1433
1464
011101 (29)
1390
1469
1422
1447
011100 (28)
1362
1443
1391
1423
011011 (27)
1352
1429
1380
1407
011010 (26)
1325
1405
1352
1385
011001 (25)
1314
1390
1340
1369
011000 (24)
1290
1368
1315
1350
010111 (23)
1276
1351
1302
1332
010110 (22)
1253
1331
1277
1313
010101 (21)
1239
1313
1264
1295
010100 (20)
1183
1255
1205
1240
010011 (19)
1204
1275
1227
1259
010010 (18)
1151
1221
1172
1207
010001 (17)
1171
1240
1193
1224
010000 (16)
1148
1218
1170
1204
001111 (15)
1137
1204
1159
1189
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Typ at 25°C
Typ over Temp
PLL Band Select
fLOW
fHIGH
fLOW
fHIGH
001110 (14)
1116
1184
1137
1170
001101 (13)
1106
1171
1127
1157
001100 (12)
1086
1152
1106
1138
001011 (11)
1075
1138
1095
1124
001010 (10)
1055
1119
1075
1106
001001 (9)
1045
1107
1065
1093
001000 (8)
1027
1090
1047
1076
000111 (7)
1016
1076
1034
1062
000110 (6)
998
1059
1016
1046
000101 (5)
987
1046
1005
1032
000100 (4)
960
1017
977
1004
000011 (3)
933
989
949
976
000010 (2)
908
962
923
950
000001 (1)
883
936
898
925
000000 (0)
859
911
873
899
VCO Frequency Ranges
Because the PLL band covers greater than a 2× frequency range,
there can be two options for the PLL band select: one at the low
end of the range and one at the high end of the range. Under
these conditions, the VCO phase noise is optimal when the user
selects the band select value corresponding to the high end of the
frequency range. Figure 75 shows how the VCO bandwidth and
the optimal VCO frequency varies with the band select value.
VCO Frequency Ranges over Temperature
The specifications given over temperature in Table 18 are for a
single part in a single lot. Part-to-part, and lot-to-lot, these
specifications can exhibit a mean shift of several register
settings. Systems should be designed to take this potential shift
into account to maintain optimal PLL performance.
PLL Loop Filter Bandwidth
The loop filter bandwidth of the PLL is programmed via SPI
Register 0x0A, Bits<4:0>. Changing these values switches
capacitors on the internal loop filter. No external loop filter
components are required. This loop filter has a pole at 0 (P1),
and then a zero (Z1) pole (P2) combination. Z1 and P2 occur
within a decade of each other. The location of the zero pole is
determined by Bits<4:0>. For a setting of 00000, the zero pole
occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2
combination can be lowered to approximately 1 MHz. The
relationship between Bits<4:0> and the position of the zero pole
between 1 MHz and 10 MHz is linear. The internal components
are not low tolerance, however, and can drift by as much as ±30%.
For optimal performance, the bandwidth adjustment
(Register 0x0A, Bits<4:0>) should be set to 11111 for all
operating modes with PLL enabled. The PLL bias settings
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