參數(shù)資料
型號： AD9776BSVZRL
廠商： Analog Devices Inc
文件頁數(shù)： 33/56頁
文件大?。?/td> 0K
描述： IC DAC 12BIT DUAL 1GSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 300mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 1G
AD9776/AD9778/AD9779
Rev. A | Page 39 of 56
voltage is 0 V to 1.6 V. When sinking current, the output
compliance voltage is 0.8 V to 1.6 V.
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 79
and Figure 80. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of
the DAC, so that ac coupling or a dc level shift is necessary. If the
required common-mode input voltage on the quadrature
modulator matches that of the DAC, then the dc blocking
capacitors in Figure 79 can be removed. A low-pass or band-pass
passive filter is recommended when spurious signals from the
DAC (distortion and DAC images) at the quadrature modulator
inputs can affect the system performance. Placing the filter at the
location shown in Figure 79 and Figure 80 allows easy design of
the filter, as the source and load impedances can easily be
designed close to 50 Ω.
05361-115
AD9779
Q DAC
AD9779
AUX
DAC2
25
Ω TO 50Ω
0.1
μF
0.1
μF
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
Q INPUTS
AD9779
I DAC
AD9779
AUX
DAC1
25
Ω TO 50Ω
0.1
μF
0.1
μF
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
I INPUTS
Figure 79. Typical Use of Auxiliary DACs AC Coupling to
Quadrature Modulator
05361-116
AD9779
I OR Q DAC
AD9779
AUX
DAC1 OR 2
25
Ω TO 50Ω
25
Ω TO 50Ω
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
I OR Q INPUTS
Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature
Modulator with DC Shift
POWER DISSIPATION
Figure 81 to Figure 89 show the power dissipation of the 1.8 V
and 3.3 V digital and clock supplies in single DAC and dual
DAC modes. In addition to this, the power dissipation/current
of the 3.3 V supply (mode and speed independent) in single
DAC mode is 102 mW/31 mA. In dual DAC mode, this is
182 mW/5
5 mA. Furthermore, when the PLL is enabled, it adds
90 mW/50 mA to the 1.8 V clock supply regardless of the mode
of the AD9779.
0
250
fDATA (MSPS)
POW
ER
(
W
)
0.6
0.7
0.5
0.4
0.3
0.2
0.1
25
50
75
100
125
150
175
200
225
8
× INTERPOLATION,
ZERO STUFFING
8
× INTERPOLATION
4
× INTERPOLATION
4
× INTERPOLATION,
ZERO STUFFING
2
× INTERPOLATION
1
× INTERPOLATION
2
× INTERPOLATION,
ZERO STUFFING
1
× INTERPOLATION,
ZERO STUFFING
05361-076
Figure 81. Total Power Dissipation, I Data Only, Real Mode
0
250
fDATA (MSPS)
POW
ER
(
W
)
0.4
25
50
75
100
125
150
175
200
225
8
× INTERPOLATION
4
× INTERPOLATION
2
× INTERPOLATION
1
× INTERPOLATION
0.3
0.2
0.1
05361-078
Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Does Not Include Zero Stuffing
0
250
fDATA (MSPS)
POW
ER
(
W
)
0.08
25
50
75
100
125
150
175
200
225
8
× INTERPOLATION
4
× INTERPOLATION
2
× INTERPOLATION
1
× INTERPOLATION
0.06
0.04
0.02
05361-079
Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
Includes Modulation Modes, Does Not Include Zero Stuffing
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