- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362132 > ADCRM Analog-to-Digital Reference Manual PDF資料下載
參數(shù)資料
| 型號： | ADCRM |
| 英文描述： | Analog-to-Digital Reference Manual |
| 中文描述： | 模擬到數(shù)字參考手冊 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 415K |
| 代理商： | ADCRM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
MOTOROLA
3-2
CONFIGURATION AND CONTROL
ADC
REFERENCE MANUAL
Execution of the CPU LPSTOP command can place the entire modular microcontrol-
ler, including the ADC, in low-power stop mode by turning off the system clock. This
command does not set the STOP bit in the ADCMCR. Before issuing the LPSTOP
command, the user should assert the STOP bit in the ADCMCR so that the module
stops in a known state.
3.2.2 Freeze Mode Operation
When the CPU enters background debugging mode, the FREEZE signal is asserted.
The ADC can respond to internal assertion of FREEZE in three ways: it can ignore
FREEZE assertion, finish the current conversion and then freeze, or freeze immedi-
ately. The type of response is determined by the value of the FRZ[1:0] field in the AD-
CMCR (see
Table 3-1
).
When the ADC freezes, the ADC clock stops and all sequential activity ceases. Con-
tents of control and status registers remain valid while frozen. When the FREEZE sig-
nal is negated, ADC activity resumes.
If the ADC freezes during a conversion, activity resumes with the next step in the con-
version sequence. However, capacitors in the analog conversion circuitry may dis-
charge while the ADC is frozen, and conversion results may be inaccurate.
3.2.3 Privilege Levels
To protect system resources, the processor in certain MCUs can operate at either of
two privilege levels: user or supervisor. In systems that support privilege levels, ac-
cesses of the ADCMCR and ADCTEST registers are permissible only when the CPU
is operating at the supervisor privilege level. The remaining ADC registers are pro-
grammable to permit supervisor access only or to permit access when the CPU is op-
erating at either privilege level.
If the SUPV bit in the ADCMCR is set, access to ADC registers is permitted only when
the CPU is operating at the supervisor level. If SUPV is clear, then both user and su-
pervisor accesses of all registers other than the ADCMCR and ADCTEST register are
permitted.
The ADC does not respond to a read or write of a supervisor-access register when the
CPU is operating at the user privilege level. Attempting such a read or write results in
the bus access being transferred externally. Refer to the SIM or SCIM section of the
appropriate MCU user's manual for details on external bus cycles to unimplemented
locations.
Table 3-1 FRZ Field Selection
FRZ
00
01
10
11
Response
Ignore FREEZE
Reserved
Finish conversion, then freeze
Freeze immediately
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADCS-1021 | ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% |
| ADCS-2021 | CMOS Image Sensors |
| ADCS-1121 | Monochrome CMOS Image Sensor (CIF) |
| ADCS-2121 | Monochrome CMOS Image Sensor (VGA) |
| ADC | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCS-1021 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:CMOS Image Sensors |
| ADCS-1120 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Agilent CMOS Monochrome Image Sensors |
| ADCS-1121 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Monochrome CMOS Image Sensor (CIF) |
| ADCS-2021 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:CMOS Image Sensors |
| ADCS-2120 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Agilent CMOS Monochrome Image Sensors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。