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參數(shù)資料
| 型號： | ADCRM |
| 英文描述： | Analog-to-Digital Reference Manual |
| 中文描述： | 模擬到數(shù)字參考手冊 |
| 文件頁數(shù)： | 25/46頁 |
| 文件大?。?/td> | 415K |
| 代理商： | ADCRM |
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ADC
REFERENCE MANUAL
DIGITAL CONTROL SUBSYSTEM
MOTOROLA
5-5
Mode 0 — A single 4-conversion sequence is performed on a single input channel
specified by the value in CD:CA. Each result is stored in a separate result register
(RSLT0 to RSLT3). The appropriate CCF bit in ADSTAT is set as each register
is filled. The SCF bit in ADSTAT is set when the conversion sequence is com-
plete.
Mode 1 — A single 8-conversion sequence is performed on a single input channel
specified by the value in CD:CA. Each result is stored in a separate result register
(RSLT0 to RSLT7). The appropriate CCF bit in ADSTAT is set as each register
is filled. The SCF bit in ADSTAT is set when the conversion sequence is com-
plete.
Mode 2 — A single conversion is performed on each of four sequential input chan-
nels, starting with the channel specified by the value in CD:CC. Each result is
stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit
in ADSTAT is set as each register is filled. The SCF bit in ADSTAT is set when
the last conversion is complete.
Mode 3 — A single conversion is performed on each of eight sequential input chan-
nels, starting with the channel specified by the value in CD. Each result is stored
in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in AD-
STAT is set as each register is filled. The SCF bit in ADSTAT is set when the last
conversion is complete.
Mode 4 — Continuous 4-conversion sequences are performed on a single input
channel specified by the value in CD:CA. Each result is stored in a separate re-
sult register (RSLT0 to RSLT3). Previous results are overwritten when a se-
quence repeats. The appropriate CCF bit in ADSTAT is set as each register is
filled. The SCF bit in ADSTAT is set when the first 4-conversion sequence is
complete.
Mode 5 — Continuous 8-conversion sequences are performed on a single input
channel specified by the value in CD:CA. Each result is stored in a separate re-
sult register (RSLT0 to RSLT7). Previous results are overwritten when a se-
quence repeats. The appropriate CCF bit in ADSTAT is set as each register is
filled. The SCF bit in ADSTAT is set when the first 8-conversion sequence is
complete.
Mode 6 — Continuous conversions are performed on each of four sequential input
channels, starting with the channel specified by the value in CD:CC. Each result
is stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF
bit in ADSTAT is set as each register is filled. The SCF bit in ADSTAT is set when
the first 4-conversion sequence is complete.
Mode 7 — Continuous conversions are performed on each of eight sequential input
channels, starting with the channel specified by the value in CD. Each result is
stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit
in ADSTAT is set as each register is filled. The SCF bit in ADSTAT is set when
the first 8-conversion sequence is complete.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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