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參數(shù)資料
| 型號： | ADCRM |
| 英文描述： | Analog-to-Digital Reference Manual |
| 中文描述： | 模擬到數(shù)字參考手冊 |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 415K |
| 代理商： | ADCRM |
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MOTOROLA
5-2
DIGITAL CONTROL SUBSYSTEM
ADC
REFERENCE MANUAL
Figure 5-1
and
Figure 5-2
illustrate the timing for 8- and 10-bit conversions, respec-
tively. These diagrams assume a final sampling period of two ADC clocks.
Figure 5-1 8-Bit Conversion Timing
Figure 5-2 10-Bit Conversion Timing
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
SCF FLAG SET HERE AND SEQUENCE
ENDS IF IN THE 4 CHANNEL MODE
SCF FLAG SET HERE AND SEQUENCE
ENDS IF IN THE 8 CHANNEL MODE
END
6 CYCLES
16
1
TRANSFER CONVERSION TO
RESULT REGISTER AND SET CCF
RESOLUTION TIME
FINAL
SAMPLE
TIME
INITIAL
SAMPLE
TIME
TRANSFER
TIME
1
CYCLE
SAR6
1
CYCLE
SAR5
1
CYCLE
SAR4
1
CYCLE
SAR3
1
CYCLE
SAR2
1
CYCLE
SAR1
1
CYCLE
SAR0
1
CYCLE
EOC
2
CYCLES
SAR7
SUCCESSIVE APPROXIMATION
SEQUENCE
SAMPLE AND TRANSFER
PERIOD
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
SCF FLAG SET HERE AND SEQUENCE
ENDS IF IN THE 4-CHANNEL MODE
SCF FLAG SET HERE AND SEQUENCE
ENDS IF IN THE 8-CHANNEL MODE
1
CYCLE
SAR8
END
6 CYCLES
16
1
TRANSFER CONVERSION TO
RESULT REGISTER AND SET CCF
RESOLUTION TIME
FINAL
SAMPLE
TIME
INITIAL
SAMPLE
TIME
TRANSFER
TIME
1
CYCLE
SAR7
1
CYCLE
SAR6
1
CYCLE
SAR5
1
CYCLE
SAR4
1
CYCLE
SAR3
1
CYCLE
SAR2
1
CYCLE
SAR1
1
CYCLE
SAR0
1
CYCLE
EOC
2
CYCLES
SAR9
SUCCESSIVE APPROXIMATION
SEQUENCE
SAMPLE AND TRANSFER
PERIOD
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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