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參數(shù)資料
| 型號： | ADCRM |
| 英文描述： | Analog-to-Digital Reference Manual |
| 中文描述： | 模擬到數(shù)字參考手冊 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 415K |
| 代理商： | ADCRM |
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MOTOROLA
4-2
ANALOG SUBSYSTEM
ADC
REFERENCE MANUAL
4.3 RC DAC Array
The RC DAC array consists of binary-weighted capacitors and a resistor-divider chain.
The array performs two functions: it acts as a sample-and-hold circuit during conver-
sion and provides each successive digital-to-analog comparison voltage to the com-
parator. Conversion begins with MSB comparison and ends with LSB comparison.
Array switching is controlled by the digital subsystem.
4.4 Comparator
The comparator indicates whether each approximation output from the RC DAC array
during resolution is higher or lower than the sampled input voltage. Comparator output
is fed to the digital control logic, which sets or clears each bit in the successive approx-
imation register in sequence, MSB first.
4.5 Successive Approximation Register (SAR)
The SAR accumulates the result of each conversion one bit at a time, starting with the
most significant bit. At the start of the resolution period, the MSB of the SAR is set, and
all less significant bits are cleared. Depending on the result of the first comparison, the
MSB is either left set or cleared. Each successive bit is set or left cleared in descend-
ing order until all eight or ten bits have been resolved.
When conversion is complete, the content of the SAR is transferred to the appropriate
result register, where it can be read by software. The SAR itself is not accessible to
user software.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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