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ADC
REFERENCE MANUAL
DIGITAL CONTROL SUBSYSTEM
MOTOROLA
5-9
MULT — Multichannel Conversion
0 = Conversion sequence(s) run on a channel selected by CD:CA.
1 = Sequential conversion of four or eight channels selected by CD:CA.
S8CM — Select Eight-Conversion Sequence Mode
0 = Four-conversion sequence
1 = Eight-conversion sequence
CD:CA — Channel Selection
The bits in this field are used to select an input or block of inputs for A/D conversion.
Table 5-5
and
Table 5-6
explain the operation of these fields.
5.7.3 ADC Status Register (ADSTAT)
ADSTAT is a read-only register that contains the sequence complete flag (SCF), con-
version counter (CCTR), and one channel converted flag (CCF) for each of the eight
channels.
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when SCAN = 0 in ADCTL1 and
set at the end of the first conversion sequence when SCAN = 1.
0 = Sequence not complete
1 = Sequence complete
CCTR[2:0] — Conversion Counter
This field shows the content of the conversion counter pointer during a conversion se-
quence. The value is the number of the next result register to be written to (i.e., the
channel currently being converted).
CCF[7:0] — Conversion Complete Flags
Each bit in this field corresponds to an A/D result register (CCF7 corresponds to
RSLT7, etc.). A bit is set when conversion of the corresponding input is complete and
is cleared when the result register containing the converted value is read.
5.8 Result Registers (RSLT0–RSLT7)
The eight read-only result registers store data after conversion is complete. Each reg-
ister can be read from three different addresses in the register block. Data format de-
pends on the address from which it is read. The result registers reside on the internal
differential data bus.
ADSTAT
— ADC Status Register
$XXXX0E
15
14
11
10
8
7
0
SCF
NOT USED
CCTR
CCF
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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