- 您現在的位置：買賣IC網 > PDF目錄9091 > ADF4193WCCPZ-RL7 (Analog Devices Inc)IC PLL FREQ SYNTHESIZER 32LFCSP PDF資料下載
參數資料
| 型號： | ADF4193WCCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Data Sheet
ADF4193
Rev. F | Page 15 of 32
FRAC/INT REGISTER (R0)
05328-023
DB23
RESERVED
0
DB22
N8
DB21
N7
DB20
N6
DB19
N5
DB18
N4
DB17
N3
DB16
N2
DB15
N1
DB14
F12
DB13
F11
DB12
F10
DB11
F9
DB10
F8
DB9
F7
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
C3 (0)
DB1
C2 (0)
DB0
C1 (0)
8-BIT RF INT VALUE
12-BIT RF FRAC VALUE
CONTROL
BITS
F12
0
.
1
F11
0
.
1
F10
0
.
1
..........
F3
0
.
1
F2
0
1
.
0
1
F1
0
1
0
1
.
0
1
0
1
FRACTIONAL VALUE (FRAC)
0
1
2
3
.
4092
4093
4094
4095
N8
0
.
1
N7
0
.
1
N6
0
.
1
N5
1
.
1
N4
1
.
1
N3
0
.
1
N2
1
.
1
N1
0
.
1
INTEGER VALUE (INT)
26
.
255
0 = < FRAC < MOD
Figure 29. FRAC/INT Register (R0)
R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the next PFD cycle following a write to
R0, the N divider section is updated with the new INT and
FRAC values. At the same time, the PLL automatically enters
fast lock mode and the charge pump current is increased to its
maximum value and stays at this value until the ICP timeout
counter times out, and switches SW1, SW2, and SW3 closed
and remains closed until the SW1, SW2, and SW3 timeout
counters time out.
Once all registers are programmed during the initialization
sequence (see Table 8), all that is required thereafter to program
a new channel is a write to R0. However, as described in the
Programming section, it can also be desirable to program R1
and R2 register settings on a channel-by-channel basis. These
settings are double buffered by the write to R0. This means
that while the data is loaded through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not updated
with their data until the next write to Register R0.
Control Bits
The three LSBs, Control Bit C3, Control Bit C2, and Control Bit C1,
should be set to 0, 0, 0, respectively, to select R0, the FRAC/INT
register.
Reserved Bit
Bit DB23 is reserved and must be set to 0.
8-Bit INT Value
These eight bits set the INT value, which determines the integer
part of the feedback division factor. All integer values from 26
to 255 are allowed. See the Worked Example section.
12-Bit FRAC Value
The 12 FRAC bits set the numerator of the fraction that is input
to the Σ-Δ modulator. This, along with INT, specifies the new
frequency channel that the synthesizer locks to, as shown in the
Worked Example section. FRAC values from 0 to MOD 1
cover channels over a frequency range equal to the PFD reference
frequency.
相關PDF資料 |
PDF描述 |
|---|---|
| V110A8H200BL3 | CONVERTER MOD DC/DC 8V 200W |
| V110A8H200BG | CONVERTER MOD DC/DC 8V 200W |
| VI-B7W-MY-F4 | CONVERTER MOD DC/DC 5.5V 50W |
| VI-B7W-MY-F3 | CONVERTER MOD DC/DC 5.5V 50W |
| MS27472E24F29S | CONN RCPT 29POS WALL MT W/SCKT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADF4196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Phase Noise, Fast Settling, 6 GHz |
| ADF4196BCPZ | 制造商:Analog Devices 功能描述:IC PLL SYNTHESIZER 32LFCSP 制造商:Analog Devices 功能描述:IC, PLL SYNTHESIZER, 32LFCSP |
| ADF4196BCPZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4206 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual RF PLL Frequency Synthesizers |
| ADF4206BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復。