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參數(shù)資料
| 型號： | ADF4193WCCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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ADF4193
Data Sheet
Rev. F | Page 16 of 32
MOD/R REGISTER (R1)
05328-
024
DB23
F5
DB22
F4
DB21
0
DB20
F2
DB19
F1
DB18
R4
DB17
R3
DB16
R2
DB15
R1
DB14
M12
DB13
M11
DB12
M10
DB11
M9
DB10
M8
DB9
M7
DB8
M6
DB7
M5
DB6
M4
DB5
M3
DB4
M2
DB3
M1
DB2
C3 (0)
DB1
C2 (0)
DB0
C1 (1)
4-BIT RF
R COUNTER
CP
ADJ
R
E
F/2
R
ESER
VED
PR
ESC
A
L
ER
DO
UBL
E
R
E
NABL
E
12-BIT MODULUS
CONTROL
BITS
0
1
NOMINAL
ADJUSTED
CP ADJ
F5
0
1
DISABLE
ENABLE
REF/2
F4
0
1
F2
4/5
8/9
PRESCALER
0
1
F1
DOUBLER DISABLED
DOUBLER ENABLED
DOUBLER ENABLE
M12
0
.
1
M11
0
.
1
M10
0
.
1
..........
M3
1
.
1
M2
0
1
.
0
1
M1
1
0
1
.
0
1
0
1
INTERPOLATOR MODULUS VALUE (MOD)
13
14
15
.
4092
4093
4094
4095
R4
0
.
1
R3
0
1
.
1
R2
0
1
0
.
0
1
R1
1
0
1
0
.
0
1
0
1
RF R COUNTER DIVIDE RATIO
1
2
3
4
.
12
13
14
15
Figure 30. MOD/R Register (R1)
This register is used to set the PFD reference frequency and the
channel step size, which is determined by the PFD frequency
divided by the fractional modulus. Note that the MOD, R
counter, REF/2, CP ADJ, and doubler enable bits are double
buffered. They do not take effect until the next write to R0
(FRAC/INT register) is complete.
Control Bits
With C3, C2, and C1 set to 0, 0, 1, respectively, the MOD/R
register (R1) is programmed.
CP ADJ
When this bit is set to 1, the charge pump current is scaled up
25% from its nominal value on the next write to R0. When this
bit is set to 0, the charge pump current stays at its nominal value
on the next write to R0. See the Programming section for more
information on how this feature can be used.
REF/2
Setting this bit to 1 inserts a divide-by-2, toggle flip-flop between
the R counter and PFD, which extends the maximum REFIN
input rate.
Reserved Bit
Reserved Bit DB21 must be set to 0.
Doubler Enable
Setting this bit to 1 inserts a frequency doubler between REFIN
and the 4-bit R counter. Setting this bit to 0 bypasses the doubler.
4-Bit RF R Counter
It allows the REFIN frequency to be divided down to produce the
reference clock to the PFD. All integer values from 1 to 15 are
allowed. See the Worked Example section.
12-Bit Interpolator Modulus
For a given PFD reference frequency, the fractional deno-
minator or modulus sets the channel step resolution at the
RF output. All integer values from 13 to 4095 are allowed.
See the Programming section for additional information and
guidelines for selecting the value of MOD.
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