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參數(shù)資料
| 型號(hào)： | ADF4193WCCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADF4193
Rev. F | Page 17 of 32
PHASE REGISTER (R2)
05328-025
DB15
0
DB14
P12
DB13
P11
DB12
P10
DB11
P9
DB10
P8
DB9
P7
DB8
P6
DB7
P5
DB6
P4
DB5
P3
DB4
P2
DB3
P1
DB2
C3 (0)
DB1
C2 (1)
DB0
C1 (0)
RESERVED
12-BIT PHASE
CONTROL
BITS
P12
0
.
1
P11
0
.
1
P10
0
.
1
..........
P3
0
.
1
P2
0
1
.
0
1
P1
0
1
0
.
0
1
0
1
PHASE VALUE1
0
1
2
.
4092
4093
4094
4095
10 = < PHASE VALUE < MOD
Figure 31. Phase Register (R2)
12-Bit Phase
The phase word sets the seed value of the Σ-Δ modulator. It can
be programmed to any integer value from 0 to MOD. As the
phase word is swept from 0 to MOD, the phase of the VCO
output sweeps over a 360° range in steps of 360°/MOD.
Note that the phase bits are double buffered. They do not take
effect until the LE of the next write to R0 (FRAC/INT register).
Therefore, if it is desired to change the phase of the VCO output
frequency, it is necessary to rewrite the INT and FRAC values to
R0, following the write to R2.
The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.
If it is desired to keep the output at the same phase offset with
respect to the reference, each time that particular output
frequency is programmed, then the interval between writes to
R0 must be an integer multiple of MOD reference cycles.
If it is desired to keep the outputs of two ADF4193-based
synthesizers phase coherent with each other, but not necessarily
with their common reference, then it is only required to ensure
that the write to R0 on both chips is performed during the same
reference cycle. The interval between R0 writes in this case does
not have to be an integer multiple of the MOD cycles.
Reserved Bit
The reserved bit, Bit DB15, should be set to 0.
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