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參數(shù)資料
| 型號(hào)： | ADN2818ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADN2817/ADN2818
Data Sheet
Rev. E | Page 18 of 40
TERMINOLOGY
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the logic
output of the quantizer and the analog voltage input is shown in
Figure 23. For sufficiently large positive input voltages, the output
is always Logic 1 and, similarly for negative inputs, the output is
always Logic 0. However, the transitions between Output Logic
Level 1 and Output Logic Level 0 are not at precisely defined
input voltage levels but occur over a range of input voltages. Within
this range of input voltages, the output may be either 1 or 0, or
it may even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage. Input
overdrive is the magnitude of signal required to guarantee the
correct logic level with 1 × 1010 confidence level.
NOISE
OUTPUT
INPUT (V p-p)
OFFSET
OVERDRIVE
SENSITIVITY
(2× OVERDRIVE)
1
0
06
00
1-
0
12
Figure 23. Input Sensitivity and Input Overdrive
SINGLE-ENDED vs. DIFFERENTIAL
AC coupling is typically used to drive the inputs to the quantizer.
The inputs are internally dc biased to a common-mode potential
of ~2.5 V. Driving the ADN2817/ADN2818 single-ended and
observing the quantizer input with an oscilloscope probe at the
point indicated in Figure 24 shows a binary signal with an average
value equal to the common-mode potential and instantaneous
values both above and below the average value. It is convenient
to measure the peak-to-peak amplitude of this signal and call
the minimum required value the quantizer sensitivity. Referring
to Figure 24, because both positive and negative offsets need to
be accommodated, the sensitivity is twice the overdrive. The
ADN2817 quantizer typically has 5 mV p-p sensitivity. The
ADN2818 does not have a limiting amplifier at its input. The
input sensitivity for the ADN2818 is 200 mV p-p.
+
–
QUANTIZER
50
3k
2.5V
VREF
SCOPE
PROBE
PIN
VREF
10mV p-p
06
00
1-
0
13
Figure 24. Single-Ended Sensitivity Measurement
Differentially driving the ADN2817 (see Figure 25), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a single-
ended probe. A 5 mV p-p signal appears to drive the ADN2817
quantizer. However, the single-ended probe measures only half
the signal. The true quantizer input signal is twice this value
because the other quantizer input is a complementary signal to
the signal being observed.
SCOPE
PROBE
PIN
50
3k
2.5V
50
VREF
QUANTIZER
+
–
NIN
5mV p-p
VREF
5mV p-p
VREF
06
00
1-
01
4
Figure 25. Differential Sensitivity Measurement
LOS RESPONSE TIME
The LOS response time is the delay between the removal of the
input signal and the indication of the loss of signal at the LOS
output, Pin 22. When the inputs are dc-coupled, the LOS assert
time of the ADN2817 is 450 ns typically and the deassert time is
500 ns typically. In practice, the time constant produced by the
ac coupling at the quantizer input and the 50 Ω on-chip input
termination determine the LOS response time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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