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參數(shù)資料
| 型號： | ADN2818ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADN2817/ADN2818
Data Sheet
Rev. E | Page 26 of 40
If the user exceeds the highest subaddress while reading back in
auto-increment mode, the highest subaddress register contents
continue to be output until the master device issues a no acknowl-
edge. This indicates the end of a read. In a no acknowledge
condition, the SDA line is not pulled low on the ninth pulse. See
Figure 19 and Figure 20 for sample read and write data transfers
and Figure 21 for a more detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2817/ADN2818. However, support for
an optional reference clock is provided. The reference clock can
be driven differentially or single-ended. If the reference clock is not
used, tie REFCLKP to VCC, and either leave REFCLKN floating or
tie it to VEE (the inputs are internally terminated to VCC/2). See
Figure 33 through Figure 35 for sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility. Phase
noise and duty cycle of the reference clock are not critical and
100 ppm accuracy is sufficient.
BUFFER
100k
VCC/2
10
11
REFCLKN
REFCLKP
ADN2817/ADN2818
06
00
1-
02
1
Figure 33. Differential REFCLK Configuration
BUFFER
100k
VCC/2
10
11
REFCLKN
REFCLKP
ADN2817/ADN2818
CLK
OSC OUT
VCC
06
00
1-
02
2
Figure 34. Single-Ended REFCLK Configuration
BUFFER
100k
VCC/2
10
11
REFCLKN
REFCLKP
ADN2817/ADN2818
VCC
06
00
1-
02
3
Figure 35. No REFCLK Configuration
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2817/ADN2818 to lock onto data, or to measure the fre-
quency of the incoming data to within 0.01%. (There is the
capability to measure the data rate to approximately ±10%
without the use of a reference clock.) The modes are mutually
exclusive because, in the first use, the user knows exactly what
the data rate is and wants to force the part to lock onto only that
data rate; in the second use, the user does not know what the
data rate is and wants to measure it.
Lock to reference mode is enabled by writing 1 to I2C Register
Bit CTRLA[0]. Data rate readback mode is enabled by writing 1
to I2C Register Bit CTRLA[1]. Writing a 1 to both of these bits at
the same time causes an indeterminate state and is not supported.
Using the Reference Clock to Lock onto Data
Writing CTRLA[0] = 1 puts the ADN2817/ADN2818 into lock
to REFCLK (LTR) mode. In this mode, the ADN2817/ADN2818
lock onto a frequency derived from the reference clock according
to the following equation:
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The user must know exactly what the data rate is and provide
a reference clock that is a function of this rate. The ADN2817/
ADN2818 can still be used as continuous rate devices in this
configuration if a reference clock with a variable frequency is
provided (see the AN-632 Application Note).
The reference clock can be anywhere between 10 MHz and
200 MHz. By default, the ADN2817/ADN2818 expect a reference
clock of between 10 MHz and 25 MHz. If it is between 25 MHz
and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz,
the user needs to configure the ADN2817/ADN2818 to use the
correct reference frequency range by setting two bits of the
CTRLA register, CTRLA[7:6].
Table 17. CTRLA[7:6] (fREF Range) with CTRLA[5:2]
(DIV_FREF Ratio) Settings
CTRLA[7:6]
Range (MHz)
CTRLA[5:2]
Ratio
00
10 to 25
0000
1
01
25 to 50
0001
2
10
50 to 100
n
2n
11
100 to 200
1000
256
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| ADN2819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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