參數(shù)資料
型號(hào)： ADN2818ACPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/40頁(yè)
文件大小： 0K
描述： IC CLOCK/DATA RECOVERY 32-LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 是
主要目的： SONET/SDH
輸入： CML
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.7GHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
ADN2817/ADN2818
Data Sheet
Rev. E | Page 24 of 40
SAMPLE PHASE ADJUST
If the user is not using the BER monitoring function, sample
phase adjustment can be used to optimize the horizontal samp-
ling point of the incoming data eye. The ADN2817 automatically
centers the sampling point to the best of its ability. However,
sample phase adjustment can be used to compensate for any
static phase offset of the CDR and data eye jitter profile asymmetry.
Sample phase adjustment is applied to the incoming eye via the
phase register. The sampling phase can be adjusted by ±0.5 UI,
in 6 degree steps, relative to the normal CDR data sampling
instant. Using the sample phase adjustment capability uses an
additional 160 mW of power. The AN-941 application note
gives additional information on the use of this feature.
BIT ERROR RATE (BER) MONITOR
The ADN2817 has a BER measurement feature that estimates
the actual bit error rate of the IC. This feature also allows data
eye jitter profiling and Q-factor estimation.
By knowing the BER at a sampling phase offset from the ideal
sampling phase (known as pseudo BER [PBER] values), it is
possible to extrapolate to obtain an estimate of the BER at the
actual sampling instant. This extrapolation relies on the assumption
that the input jitter is composed of deterministic and random
(Gaussian) components. The implementation requires off-chip
control and data processing to estimate the actual BER. A lower
accuracy voltage output mode is also supported that requires no
data processing or I2C control.
Brief Overview of Modes of Operation
The following two modes of operation are available for the BER
feature: the BER extrapolation mode and the voltage output mode.
Only one mode can be operational at a time. The BER extra-
polation mode scans the input eye in the range of ±0.5 UI of the
data center and reads the measured PBER over the I2C. The user
then applies a data processing algorithm to determine the BER.
Using the BER feature in this way provides for the greatest accuracy
in BER estimation as the magnitude of both random (Gaussian)
jitter and deterministic jitter can be estimated and used to predict
the actual BER.
In the voltage output mode, the part autonomously samples the
PBER at 0.1 UI offset and decodes this value to provide an estimate
of the input BER. This estimate is output via a DAC as an analog
current output. The AN-941 application note gives detailed
information on the use of the BER monitor features.
BER Extrapolation Mode
Power Saving
The following three power settings are available in BER
extrapolation mode: BER off, BER on, and BER standby.
In BER off mode (BERCTLB[5] = 0), the BER circuitry is
powered down with the ADN2817 providing normal CDR
operation.
In BER on mode (BERCTLB[5] = 1), the internal BER circuitry
is powered up. The user can perform pseudo BER measurements
through the I2C.
In BER standby mode (BERCTLB[5:4] = 11b), the BER is placed
into a lower power mode. This setting can only be set after
applying the BER on setting.
These modes are defined to allow optimal power saving
opportunities. It is not possible to switch between the BER
off setting and the BER on setting without losing lock. Switching
between the BER standby setting and the BER on setting is
achieved without interrupting data recovery. The incremental
power between the BER off setting and the BER standby setting
is 77 mW and between the BER off setting and the BER on setting
it is 160 mW.
BER On Mode
The BER on mode allows the user to scan the incoming data eye
in the time dimension and build up a profile of the BER statistics.
The following is a brief overview of user protocol:
The user powers up BER circuitry through the I2C.
The user initiates the PBER measurement. Sample phase offset
and number of data bits to be counted (NUMBITS is a choice
among 218, 221, 224, 227, 230, 233, 236, and 239) are supplied by the
user through the I2C.
The user initiates the pseudo BER measurement by writing
a 1-to-0 transition on BERCTLA[3].
BER logic indicates the end of the BER measurement with
an EOBM signal and updates the number of counted errors
on NUMERRORS[39:0]. The user must poll the I2C to
determine if the EOBM bit, BERSTS[0], has been asserted.
The user reads back NUMERRORS[39:0] through the I2C.
NUMERRORS[39:0] is read back through the 8-bit register
BER_RES at Address 0x21. The user sets BERCTLA[2:0] to
address one of the five NUMERRORS bytes and then reads
the selected byte from BER_RES.
PBER for programmed sample phase is calculated as
NUMERRORS/NUMBITS.
The user initiates another PBER measurement.
The user sweeps the phase over 0.5 UI to +0.5 UI with
respect to the normal sampling instant to obtain the BER
profile required.
The ADN2817 does not output the BER at the normal decision
instant. It outputs PBER measurements to the left and right of
the normal decision instants from which the user must calculate
what the BER is at the normal decision instant. A microprocessor is
required to parse the data and to use the remaining data for BER
estimation. Suitable algorithms are suggested in the AN-941
Application Note, BER Monitor User Guide.
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