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參數(shù)資料
| 型號： | ADN2818ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADN2817/ADN2818
Rev. E | Page 23 of 40
HARMONIC DETECTOR
The ADN2817/ADN2818 provide a harmonic detector, which
detects whether the input data has changed to a lower harmonic
of the data rate onto which the VCO is currently locked. For
example, if the input data instantaneously changes from an OC-48,
2.488 Gbps to an OC-12, 622.080 Mbps bit stream, this could be
perceived as a valid OC-48 bit stream, because the OC-12 data
pattern is exactly 4× slower than the OC-48 pattern. Therefore,
if the change in data rate is instantaneous, a 101 pattern at OC-12 is
perceived by the ADN2817/ADN2818 as a 111100001111 pattern
at OC-48. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2817/ADN2818 implement a harmonic detector that
automatically identifies whether the input data has switched to a
lower harmonic of the data rate onto which the VCO is currently
locked. When a harmonic is identified, the LOL pin is asserted
and a new frequency acquisition is initiated. The ADN2817/
ADN2818 automatically lock onto the new data rate, and the
LOL pin is deasserted.
However, the harmonic detector does not detect higher har-
monics of the data rate. If the input data rate switches to a
higher harmonic of the data rate onto which the VCO is currently
locked, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2817/ADN2818
automatically lock onto the new data rate.
The time to detect lock to harmonic is
16,384 × (Td/ρ)
where:
1/Td is the new data rate. For example, if the data rate is switched
from OC-48 to OC-12, then Td = 1/622 MHz.
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS or 8b/10b encoding.
When the ADN2817/ADN2818 is placed in lock to reference
mode, the harmonic detector is disabled.
LIMITING AMPLIFIER (ADN2817 ONLY)
The limiting amplifier on the ADN2817 has differential inputs
(PIN/NIN) that internally terminate with 50 Ω to an on-chip
voltage reference (VREF = 2.5 V typically). The inputs are typically
ac-coupled externally, although dc coupling is possible as long
as the input common-mode voltage remains above 2.5 V (see
Figure 40, Figure 41, and Figure 42). Input offset is factory
trimmed to achieve better than 6 mV typical sensitivity with
minimal drift. The limiting amplifier can be driven differentially
or single-ended.
SLICE LEVEL ADJUST (ADN2817 ONLY)
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or duty
cycle distortion by applying a differential voltage input of up to
±0.95 V to SLICEP/SLICEN inputs. If no adjustment of the slice
level is needed, SLICEP/SLICEN should be tied to VEE. The gain
of the slice adjustment is ~0.1 V/V.
LOSS OF SIGNAL (LOS) DETECTOR
(ADN2817 ONLY)
The receiver front-end LOS detector circuit detects when the input
signal level has fallen below a user-adjustable threshold. The
threshold is set with a single external resistor from Pin 9, THRADJ,
to VEE. The LOS comparator trip point vs. resistor value is shown
in Figure 6. If the input level to the ADN2817 drops below the
programmed LOS threshold, the output of the LOS detector, Pin 22
(LOS), is asserted to a Logic 1. The LOS detector response time is
450 ns by design but is dominated by the RC time constant in ac-
coupled applications. The LOS pin defaults to active high.
However, by setting Bit CTRLC[2] to 1, the LOS pin is configured
as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means that,
if the input level drops below the programmed LOS threshold
causing the LOS pin to assert, the LOS pin is not deasserted until
the input level has increased to 6 dB (2×) above the LOS threshold
(see Figure 31).
06
00
1-
0
20
HYSTERESIS
LOS OUTPUT
INPUT LEVEL
LOS THRESHOLD
t
IN
PU
T
VO
LT
A
G
E
(
V
DI
F
)
Figure 31. ADN2817 LOS Detector Hysteresis
The LOS detector and the slice level adjust can be used simul-
taneously on the ADN2817. This means that any offset added to
the input signal by the slice adjust pins does not affect the LOS
detector measurement of the absolute input level.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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