參數(shù)資料
型號(hào)： ADN2818ACPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK/DATA RECOVERY 32-LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 是
主要目的： SONET/SDH
輸入： CML
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.7GHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
ADN2817/ADN2818
Data Sheet
Rev. E | Page 20 of 40
THEORY OF OPERATION
The ADN2817/ADN2818 are delay- and phase-locked loop
circuits for clock recovery and data retiming from an NRZ
encoded data stream. The phase of the input data signal is tracked
by two separate feedback loops that share a common control
voltage. A high speed delay-locked loop path uses a voltage
controlled phase shifter to track the high frequency components
of input jitter. A separate phase control loop, composed of the
VCO, tracks the low frequency components of input jitter. The
initial frequency of the VCO is set by a third loop, which
compares the VCO frequency with the input data frequency
and sets the coarse tuning voltage. The jitter tracking phase-
locked loop controls the VCO by the fine-tuning control.
The delay- and phase-locked loops together track the phase of
the input data signal. For example, when the clock lags input
data, the phase detector drives the VCO to a higher frequency
and increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while, simultaneously, the
delayed data loses phase. Because the loop filter is an integrator,
the static phase error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 28 shows that
the jitter transfer function, Z(s)/X(s), is second-order low-pass,
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 29). This makes this circuit ideal for signal regene-
rator applications, where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
X(s)
Z(s)
RECOVERED
CLOCK
e(s)
INPUT
DATA
d/sc
psh
o/s
1/n
d
= PHASE DETECTOR GAIN
o
= VCO GAIN
c
= LOOP INTEGRATOR
psh
= PHASE SHIFTER GAIN
n
= DIVIDE RATIO
=
1
cn
do
s2
+
n psh
o
s
+ 1
Z
(s)
X
(s)
JITTER TRANSFER FUNCTION
=
s2
d psh
c
s
++
do
cn
e
(s)
X
(s)
TRACKING ERROR TRANSFER FUNCTION
06
00
1-
0
17
Figure 28. ADN2817/ADN2818 PLL/DLL Architecture
ADN28xx
Z(s)
X(s)
FREQUENCY (kHz)
JITTER PEAKING
IN ORDINARY PLL
JI
T
E
R
G
A
IN
(
d
B)
o
n psh
d psh
c
06
00
1-
01
8
Figure 29. ADN2817/ADN2818 Jitter Response vs. Conventional PLL
The delay- and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to track
large jitter amplitudes with small phase error. In this case, the
VCO is frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider tuning
range gives larger accommodation of low frequency jitter. The
internal loop control voltage remains small for small phase
errors, so the phase shifter remains close to the center of its
range and thus contributes little to the low frequency jitter
accommodation.
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