參數(shù)資料
型號(hào): ADSP-21160NCBZ-100
廠商: Analog Devices Inc
文件頁數(shù): 5/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 400-PBGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,連接端口,串行端口
時(shí)鐘速率: 100MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.90V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 400-BBGA
供應(yīng)商設(shè)備封裝: 400-PBGA(27x27)
包裝: 托盤
–13–
REV. 0
ADSP-21160N
CLK_CFG3–0
I
Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal
to n
CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the
RESET & CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.
CLKOUT
O/T
CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can
be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled
on the ADSP-21160N with ID2-0 = 00x). Do not use CLKOUT in multiprocessing
systems; use CLKIN instead.
RESET
I/A
Processor Reset. Resets the ADSP-21160N to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k
internal pull-up resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
20 k
internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine.
TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21160N.
TRST has a
20 k
internal pull-up resistor.
EMU
O (O/D)
Emulation Status. Must be connected to the ADSP-21160N emulator target board
connector only.
EMU has a 50 k
internal pull-up resistor.
CIF
O/T
Core Instruction Fetch. Signal is active low when an external instruction fetch is
performed. Driven by bus master only. Three-state when host is bus master.
CIF has a
20 k
internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
VDDINT
P
Core Power Supply. Nominally 1.9 V dc and supplies the DSP’s core processor
(40 pins).
VDDEXT
P
I/O Power Supply. Nominally 3.3 V dc (43 pins).
AVDD
P
Analog Power Supply. Nominally 1.9 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as VDDINT, except that added filtering
circuitry is required. For more information, see Power Supplies on Page 8.
AGND
G
Analog Power Supply Return.
GND
G
Power Supply Return (82 pins).
NC
Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).
Table 3. Boot Mode Selection
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect
BMS to EPROM chip select.)
0
1 (Input)
Host Processor
0
1
1 (Input)
Link Port
0
0 (Input)
No Booting. Processor executes from external memory.
0
1
0 (Input)
Reserved
1
x (Input)
Reserved
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
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