Timing Requirements tRSTVDD" />
參數(shù)資料
型號: ADSP-21160NCBZ-100
廠商: Analog Devices Inc
文件頁數(shù): 9/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 400-PBGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,連接端口,串行端口
時鐘速率: 100MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.90V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 400-BBGA
供應(yīng)商設(shè)備封裝: 400-PBGA(27x27)
包裝: 托盤
–17–
REV. 0
ADSP-21160N
Table 4. Power-up Sequencing
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before V
DDINT/VDDEXT on
0
ns
tIVDDEVDD
VDDINT on Before VDDEXT
– 50
+ 200
ms
tCLKVDD
CLKIN Running After valid VDDINT/VDDEXT
1
0
200
ms
tCLKRST
CLKIN Valid Before
RESET Deasserted
10
2
s
tPLLRST
PLL Control Setup Before
RESET Deasserted
20
3
s
Switching Characteristics
tCORERST
DSP Core Reset Deasserted After
RESET Deasserted
4096tCK
3, 4
ms
1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.9 V and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds
of milliseconds, depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time.
3 Based on CLKIN cycles.
4
CORERST is an internal signal only. The 4096 cycle count is dependent on tSRST specification. If setup time is not met, one additional CLKIN cycle may
be added to the core reset time, resulting in 4097 cycles maximum.
Figure 6. Power-up Sequencing
Figure 7. Dual Voltage Schottky Diode
CLKIN
RESET
tRSTVDD
VDDEXT
VDDINT
tIVDDEVDD
tCLKVDD
tCLKRST
tPLLRST
tCORERST
CLK_CFG3-0
CORERST
3.3V I/O
VOLTAGE REGULATOR
1.9V CORE
VOLTAGE REGULATOR
ADSP-21160
VDDEXT
VDDINT
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