V
參數(shù)資料
型號(hào)： ADSP-21161NCCAZ100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/60頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 225MBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 225-CSPBGA（17x17）
包裝： 托盤
其它名稱： ADSP21161NCCAZ100
Rev. C
|
Page 18 of 60
|
January 2013
ELECTRICAL CHARACTERISTICS
Parameter Description
Test Conditions
Min
Max
Unit
VOH
High Level Output Voltage1
@ VDDEXT = Min, IOH = –2.0 mA
2.4
V
VOL
Low Level Output Voltage1
@ VDDEXT = Min, IOL = 4.0 mA
0.4
V
IIH
High Level Input Current3, 4
@ VDDEXT = Max, VIN = VDDEXT Max
10
μA
IIL
Low Level Input Current3
@ VDDEXT = Max, VIN = 0 V
10
μA
IIHC
CLKIN High Level Input Current5
@ VDDEXT = Max, VIN = VDDEXT Max
35
μA
IILC
CLKIN Low Level Input Current5
@ VDDEXT = Max, VIN = 0 V
35
μA
IIKH
Keeper High Load Current6
@ VDDEXT = Max, VIN = 2.0 V
–250
–100
μA
IIKL
Keeper Low Load Current6
@ VDDEXT = Max, VIN = 0.8 V
50
200
μA
IIKH-OD
Keeper High Overdrive Current6, 7, 8
@ VDDEXT = Max
–300
μA
IIKL-OD
Keeper Low Overdrive Current6, 7, 8
@ VDDEXT = Max
300
μA
IILPU
Low Level Input Current Pull-Up4
@ VDDEXT = Max, VIN = 0 V
350
μA
IOZH
Three-State Leakage Current9, 10, 11
@ VDDEXT = Max, VIN = VDDEXT Max
10
μA
IOZL
Three-State Leakage Current9, 12, 13
@ VDDEXT = Max, VIN = 0 V
10
μA
IOZLPU1
Three-State Leakage Current Pull-Up110
@ VDDEXT = Max, VIN = 0 V
500
μA
IOZLPU2
Three-State Leakage Current Pull-Up211
@ VDDEXT = Max, VIN = 0 V
350
μA
IOZHPD1
Three-State Leakage Current Pull-Down112
@ VDDEXT = Max, VIN = VDDEXT Max
350
μA
IOZHPD2
Three-State Leakage Current Pull-Down213
@ VDDEXT = Max, VIN = VDDEXT Max
500
μA
IDD-INPEAK
Supply Current (Internal)14, 15
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
965
900
mA
IDD-INHIGH
Supply Current (Internal)15, 16
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
700
650
mA
IDD-INLOW
Supply Current (Internal)15, 17
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
535
500
mA
IDD-IDLE
Supply Current (Idle)15, 18
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
425
400
mA
AIDD
Supply Current (Analog)19
@ AVDD = Max
10
mA
CIN
Input Capacitance20, 21
fIN = 1 MHz, TCASE = 25°C, VIN = 1.8 V
4.7
pF
1 Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,
TDO, CLKOUT, TIMEXP, RSTOUT.
2 See Output Drive Currents on Page 54 for typical drive current capabilities.
3 Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.
4 Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
5 Applies to CLKIN only.
6 Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
7 Current required to switch from kept high to low or from kept low to high.
8 Characterized, but not tested.
9 Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,
BRST.
10Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.
11Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.
12Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use IOZHPD2 for Rev. 1.2 and higher.
13Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).
14The test program used to measure I
DDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 20.
15Current numbers are for V
DDINT and AVDD supplies combined.
16IDDINHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 20.
17IDDINLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 20.
18Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 20.
19Characterized, but not tested.
20Applies to all signal pins.
21Guaranteed, but not tested.
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