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參數(shù)資料
| 型號： | ADSP-21161NCCAZ100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/60頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 225MBGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 225-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | ADSP21161NCCAZ100 |
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Rev. C
|
Page 19 of 60
|
January 2013
PACKAGE INFORMATION
The information presented in Figure 7 provides details about
how to read the package brand and relate it to specific product
features.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 6 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD CAUTION
TIMING SPECIFICATIONS
The ADSP-21161N’s internal clock switches at higher frequen-
cies than the system input clock (CLKIN). To generate the
internal clock, the DSP uses an internal phase-locked loop
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the DSP’s internal clock
(the clock source for the external port logic and I/O pads).
The ADSP-21161N’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, link ports, serial ports, and external port (as required for
read/write strobes in asynchronous access mode). During reset,
program the ratio between the DSP’s internal clock frequency
and external (CLKIN) clock frequency with the CLK_CFG1–0
and CLKDBL pins. Even though the internal clock is the clock
source for the external port, it behaves as described in the Clock
Rate Ratio chart in Table 3 on Page 16. To determine switching
frequencies for the serial and link ports, divide down the inter-
nal clock, using the programmable divider control of each port
(DIVx for the serial ports and LxCLKD for the link ports).
Note the following definitions of various clock periods that are a
function of CLKIN and the appropriate ratio control (Table 7).
Figure 8 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and
8:1 with external oscillator or crystal. It also shows support for
CLKOUT-to-CLKIN ratios of 1:1 and 2:1.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See Figure 37 on Page 54 under Test Conditions for voltage ref-
erence levels.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given circum-
stance. Use switching characteristics to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Figure 7. Typical Package Brand
Table 5. Package Brand Information
Brand Key
Field Description
ADSP-21161N
Model Number
tTemperature Range
pp
Package Type
z
RoHS Compliance Option
vvvvv.x
Assembly Lot Code
n.n
Silicon Revision
#
RoHS Compliance Designation
yyww
Date Code
Table 6. Absolute Maximum Ratings
Parameter
Rating
Internal (Core) Supply Voltage (V
DDINT)
–0.3 V to +2.2 V
Analog (PLL) Supply Voltage (A
VDD)
–0.3 V to +2.2 V
External (I/O) Supply Voltage (V
DDEXT)
–0.3 V to +4.6 V
Input Voltage
–0.5 V to VDDEXT + 0.5 V
Output Voltage Swing
–0.5 V to V
DDEXT + 0.5 V
Load Capacitance
200 pF
Storage Temperature Range
–65
C to +150C
vvvvvv.x n.n
S
a
#yyww country_of_origin
ADSP-21161N
tppZ-cc
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
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| ADSP-21161NKCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21261 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Embedded Processor |
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