參數(shù)資料
型號(hào): ADSP-2171BSZ-133
廠商: Analog Devices Inc
文件頁數(shù): 21/52頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 128PQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 10kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
REV. A
–28–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Host Interface Port
Multiplexed Data and Address (HMD1 = 1)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
tHALP
ALE Pulse Width
10
ns
tHASU
HAD15–0 Address Setup before ALE Low
5
ns
tHAH
HAD15–0 Address Hold after ALE Low
2
ns
tHALS
Start of Write or Read after ALE Low
1
10
ns
tHSU
HRW Setup before Start of Write or Read
1
5ns
tHDSU
HAD15–0 Data Setup before End of Write
2
5ns
tHWDH
HAD15–0 Data Hold after End of Write
2
3ns
tHH
HRW Hold after End of Write or Read
2
3ns
tHRWP
Read or Write Pulse Width
3
20
ns
Switching Characteristic:
tHSHK
HACK
Low after Start of Write or Read
1
015
ns
tHKH
HACK
Hold after End of Write or Read
2
015
ns
tHDE
HAD15–0 Data Enabled after Start of Read
1
0ns
tHDD
HAD15–0 Data Valid after Start of Read
1
18
ns
tHRDH
HAD15–0 Data Hold after End of Read
2
0ns
tHRDD
HAD15–0 Data Disabled after End of Read
2
7ns
NOTES
1Start of Write or Read = HDS Low and HSEL Low.
2End of Write or Read = HDS High and HSEL High.
3Read or Write Pulse Width = HDS Low and HSEL Low.
ADDRESS
t
HDSU
DATA
HACK
HRW
HSEL
HD15–0
t
HRWP
t
HSHK
ALE
t
HALP
t
HALS
t
HKH
t
HAH
t
HASU
t
HWDH
HDS
t
HH
t
HSU
ADDRESS
DATA
HACK
HRW
HSEL
HD15–0
t
HRWP
t
HSHK
ALE
t
HALP
t
HALS
t
HKH
t
HAH
t
HASU
t
HRDH
HDS
t
HH
t
HSU
t
HDE
t
HDD
t
HRDD
Figure 17. Host Interface Port (HMD1 = 1, HMD0 = 1)
Host Write Cycle
Host Read Cycle
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