V
參數(shù)資料
型號： ADSP-2171BSZ-133
廠商： Analog Devices Inc
文件頁數(shù)： 9/52頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 128PQFP
標準包裝： 1
系列： ADSP-21xx
類型： 定點
接口： 主機接口，串行端口
時鐘速率： 33MHz
非易失內(nèi)存： 外部
芯片上RAM： 10kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
ADSP-2171/ADSP-2172–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
VDD
Supply Voltage
4.5
5.5
4.5
5.5
V
TAMB
Ambient Operating Temperature
0
+70
–40
+85
°C
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter
Test Conditions
Min
Max
Unit
VIH
Hi-Level Input Voltage
1, 2
@ VDD = max
2.0
V
VIH
Hi-Level CLKIN Voltage
@ VDD = max
2.2
V
VIH
Hi-Level RESET Voltage
@ VDD = max
2.2
V
VIL
Lo-Level Input Voltage
1, 3
@ VDD = min
0.8
V
VOH
Hi-Level Output Voltage
1, 4, 5
@ VDD = min
IOH = –0.5 mA
2.4
V
@ VDD = min
IOH = –100 A
6
VDD – 0.3
V
VOL
Lo-Level Output Voltage
1, 4, 5
@ VDD = min
IOL = 2 mA
0.4
V
IIH
Hi-Level Input Current
3
@ VDD = max
VIN = VDD max
10
A
IIL
Lo-Level Input Current
3
@ VDD = max
VIN = 0 V
10
A
IOZH
Tristate Leakage Current
7
@ VDD = max,
VIN = VDD max
8
10
A
IOZL
Tristate Leakage Current
7
@ VDD = max,
VIN = 0 V
8
10
A
IDD
Supply Current (Idle)
9, 10
@ VDD = max
18
mA
IDD
Supply Current (Dynamic)
10
@ VDD = max
tCK = 30 ns
11
75
mA
IDD
Supply Current (Powerdown)
10
Lowest Power Mode
12
100
A
CI
Input Pin Capacitance
3, 6, 13
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C8
pF
CO
Output Pin Capacitance
6, 7, 13, 14
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C8
pF
NOTES
1Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, HD0-HD15/HAD0-HAD15.
2Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
3Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.
4Output pins: BG, PMS, DMS, BMS, RD, WR, PWDACK, A0-A13, DT0, DT1, CLKOUT, HACK, FL2-0, BGH.
5Although specified for TTL outputs, all ADSP-2171/ADSP-2172 outputs are CMOS-compatible and will drive to V
DD and GND, assuming no dc loads.
6Guaranteed but not tested.
7Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15.
80 V on BR, CLKIN Active (to force three-state condition).
9Idle refers to ADSP-2171/ADSP-2172 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD or GND. Current reflects
device operation with CLKOUT disabled.
10Current reflects device operating with no output loads.
11V
IN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.
12See Chapter 9, of the ADSP-2100 Family User’s Manual for details.
13Applies to TQFP and PQFP package types.
14Output pin capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
ADSP-2171/ADSP-2172/ADSP-2173
–17–
REV. A
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