tCK
參數(shù)資料
型號: ADSP-2171BSZ-133
廠商: Analog Devices Inc
文件頁數(shù): 27/52頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128PQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 10kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–33–
ADSP-2173
Parameter
Min
Max
Unit
Clock Signals
tCK is defined as 0.5 tCKI. The ADSP-2173 uses an input clock with
a frequency equal to half the instruction rate; a 10.0 MHz input
clock (which is equivalent to 100 ns) yields a 50 ns processor cycle
(equivalent to 20 MHz). tCK values within the range of 0.5 tCKI
period should be substituted for all relevant timing parameters
to obtain specification value.
Example: tCKH = 0.5tCK – 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
Timing Requirement:
tCKI
CLKIN Period
100
160
ns
tCKIL
CLKIN Width Low
20
ns
tCKIH
CLKIN Width High
20
ns
Switching Characteristic:
tCKL
CLKOUT Width Low
0.5tCK – 10
ns
tCKH
CLKOUT Width High
0.5tCK – 10
ns
tCKOH
CLKIN High to CLKOUT High
0
25
ns
Control Signals
Timing Requirement:
tRSP
RESET Width Low
5tCK
1
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKIL
t
CKOH
t
CKH
t
CKL
t
CKI
t
CKIH
Figure 24. Clock Signals
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