T
參數(shù)資料
型號(hào): ADSP-2171BSZ-133
廠商: Analog Devices Inc
文件頁(yè)數(shù): 22/52頁(yè)
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 128PQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 10kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤(pán)
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–29–
ADSP-2171/ADSP-2172
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ
CA = Thermal Resistance (Case-to-Ambient)
θ
JA = Thermal Resistance (Junction-to-Ambient)
θ
JC = Thermal Resistance (Junction-to-Case)
Package
θ
JA
θ
JC
θ
CA
TQFP
50
°C/W
2
°C/W
48
°C/W
PQFP
41
°C/W
10
°C/W
31
°C/W
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
× V
DD
2
× f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
The application operates at V
DD = 5.0 V and tCK = 30 ns.
Total Power Dissipation = PINT + (C × VDD
2
× f )
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 18).
(C
× V
DD
2
× f ) is calculated for each output:
# of
Pins
× C
× V
DD
2
× f
Address, DMS
8
× 10 pF × 52 V × 33.3 MHz = 66.6 mW
Data Output, WR 9
× 10 pF × 52 V × 16.67 MHz = 37.5 mW
RD
1
× 10 pF × 52 V × 16.67 MHz =
4.2 mW
CLKOUT
1
× 10 pF × 52 V × 33.3 MHz =
8.3 mW
116.6 mW
Total power dissipation for this example is PINT + 116.6 mW.
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-2171 STATE OF OPERATION DURING
EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE
DRIVEN TO EITHER V
DD OR GND. POWER REFLECTS DEVICE
OPERATING WITH CLKOUT DISABLED.
3 TYPICAL POWER DISSIPATION AT 5.0V V
DD DURING EXECUTION
OF
IDLE N INSTRUCTION (CLOCK FREQUENCY REDUCTION).
POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.
POWER, INTERNAL
V
DD
= 4.5V
186mW
382mW
229mW
148mW
110mW
27
23
21
19
17
15
25
13
31
29
33
V
DD
= 5.0V
V
DD
= 5.5V
225
175
200
300
250
275
325
375
350
400
150
125
301mW
POWER
(P
INT
)–
mW
1
/ t
CK
– MHz
POWER
(P
IDLE
)–
mW
POWER, IDLE
50
40
45
65
55
60
70
80
75
85
35
30
27
23
21
19
17
15
25
13
31
29
33
1
/ t
CK
– MHz
48mW
37mW
26mW
82mW
48mW
64mW
V
DD
= 4.5V
V
DD
= 5.0V
V
DD
= 5.5V
IDLE;
IDLE (16)
IDLE (128)
27
23
21
19
17
15
25
13
31
29
33
1
/ t
CK
– MHz
POWER
(P
IDLE
n
)–
mW
POWER,
IDLE n MODES
82mW
20mW
37mW
23mW
31mW
64mW
44
36
40
56
48
52
60
68
64
72
32
28
24
20
16
28mW
3
1, 2
1
Figure 18. Power vs. Frequency
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