參數(shù)資料
型號(hào)： ADSP-2171BSZ-133
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/52頁(yè)
文件大小： 0K
描述： IC DSP CONTROLLER 16BIT 128PQFP
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類(lèi)型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 33MHz
非易失內(nèi)存： 外部
芯片上RAM： 10kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤(pán)
REV. A
–30–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
CAPACITIVE LOADING
Figures 19 and 20 show the capacitive loading characteristics of
the ADSP-2171/ADSP-2172.
RISE
TIME
(0.4V
-
2.4V)
–
ns
28
12
4
8
24
16
20
25
150
125
100
75
50
C
L
– pF
V
DD
= 4.5V
Figure 19. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
+14
+4
–2
+2
+12
+8
+10
25
150
125
100
75
50
C
L
– pF
NOMINAL
VALID
OUTPUT
DELAY
OR
HOLD
–
ns
Figure 20. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low volt-
age level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the
following equation:
t
DECAY =
C
L 0.5 V
i
L
from which
t
DIS = t MEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
3.0V
1.5V
0.0V
2.0V
1.5V
0.3V
INPUT
OUTPUT
Figure 21. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start driv-
ing. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
Figure 22. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
I
OH
I
OL
Figure 23. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
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