參數(shù)資料
型號: ADSP-BF535PKBZ-300
廠商: Analog Devices Inc
文件頁數(shù): 10/44頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 260 BGA
產(chǎn)品培訓模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: PCI,SPI,SSP,UART,USB
時鐘速率: 300MHz
非易失內(nèi)存: 外部
芯片上RAM: 308kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 260-BBGA
供應商設備封裝: 260-PBGA(19x19)
包裝: 托盤
ADSP-BF535
–18–
REV. A
PF4/
SPI0SEL2/MSEL4 I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF3/
SPI1SEL1/MSEL3 I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF2/
SPI0SEL1/MSEL2 I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF1/
SPISS1/MSEL1
I/O
Programmable flag pin. SPI slave select input pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF0/
SPISS0/MSEL0
I/O
Programmable flag pin. SPI slave select input pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
RSCLK0
I/O/T Receive serial clock for SPORT0.
RFS0
I/O/T Receive frame synchronization for SPORT0.
DR0
I
Serial data receive for SPORT0.
TSCLK0
I/O/T Transmit serial clock for SPORT0.
TFS0
I/O/T Transmit frame synchronization for SPORT0.
DT0
O
Serial data transmit for SPORT0.
RSCLK1
I/O/T Receive serial clock for SPORT1.
RFS1
I/O/T Receive frame synchronization for SPORT1.
DR1
I
Serial data receive for SPORT1.
TSCLK1
I/O/T Transmit serial clock for SPORT1.
TFS1
I/O/T Transmit frame synchronization for SPORT1.
DT1
O
Serial data transmit for SPORT1.
MOSI0
I/O
Master out slave in pin for SPI0. Supplies the output data from the master device and
receives the input data to a slave device.
MISO0
I/O
Master in slave out pin for SPI0. Supplies the output data from the slave device and
receives the input data to the master device.
SCK0
I/O
Clock line for SPI0. Master device output clock signal. Slave device input clock signal.
MOSI1
I/O
Master out slave in pin for SPI1. Supplies the output data from the master device and
receives the input data to a slave device.
MISO1
I/O
Master in slave out pin for SPI1. Supplies the output data from the slave device and
receives the input data to the master device.
SCK1
I/O
Clock line for SPI1. Master device output clock signal. Slave device input clock signal.
RX0
I
UART0 receive pin.
TX0
O
UART0 transmit pin.
RX1
I
UART1 receive pin.
TX1
O
UART1 transmit pin.
USB_CLK
I
USB clock.
XVER_DATA
I
Single ended receive data output from USB transceiver to the USBD module.
DPLS
I
Differential D+ receive data output from the USB transceiver to the UBD module.
DMNS
I
Differential D- receive data output from the USB transceiver to the USBD module.
TXDPLS
O
Transmitted D+ from the USBD module to the USB transceiver.
TXDMNS
O
Transmitted D- from the USBD module to the USB transceiver.
TXEN
O
Transmit enable from the USBD module to the USB transceiver.
SUSPEND
O
Suspend mode enable output from the USBD module to the USB transceiver.
NMI
I
Non-maskable interrupt.
TCK
I
JTAG clock.
TDO
O/T
JTAG serial data out.
TDI
I
JTAG serial data in.
TMS
I
Test mode select.
Table 7. Pin Descriptions (continued)
Pin
Type
Function
Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state
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