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參數(shù)資料
| 型號： | ADSP-BF535PKBZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/44頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 260 BGA |
| 產(chǎn)品培訓(xùn)模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | PCI，SPI，SSP，UART，USB |
| 時(shí)鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 308kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 260-BBGA |
| 供應(yīng)商設(shè)備封裝： | 260-PBGA（19x19） |
| 包裝： | 托盤 |
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–13–
REV. A
ADSP-BF535
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than 40%.
Further, these power savings are additive, in that if the clock
frequency and power are both reduced, the power savings are
dramatic.
Dynamic Power Management allows both the processor’s input
voltage (VDDINT) and clock frequency (fCCLK) to be dynamically
and independently controlled.
As previously explained, the savings in power dissipation can be
modeled by the following equation:
where:
is the nominal core clock frequency (300 MHz)
is the reduced core clock frequency
is the nominal internal supply voltage (1.5 V)
is the reduced internal supply voltage
As an example of how significant the power savings of Dynamic
Power Management are when both frequency and voltage are
reduced, consider an example where the frequency is reduced
from its nominal value to 50 MHz and the voltage is reduced from
its nominal value to 1.2 V. At this reduced frequency and voltage,
the processor dissipates about 10% of the power dissipated at
nominal frequency and voltage.
Peripheral Power Control
The ADSP-BF535 Blackfin processor provides additional power
control capability by allowing dynamic scheduling of clock inputs
to each of the peripherals. Clocking to each of the peripherals
listed below can be enabled or disabled by appropriately setting
the peripheral’s control bit in the peripheral clock enable register
(PLL_IOCK). The Peripheral Clock Enable Register allows indi-
vidual control for each of these peripherals:
PCI
EBIU controller
Programmable flags
MemDMA controller
SPORT 0
SPORT 1
SPI 0
SPI 1
UART 0
UART 1
Timer 0, Timer 1, Timer 2
USB CLK
Clock Signals
The ADSP-BF535 Blackfin processor can be clocked by a sine
wave input or a buffered shaped clock derived from an external
clock oscillator.
If a buffered, shaped clock is used, this external clock connects
to the processor CLKIN pin. The CLKIN input cannot be
halted, changed, or operated below the specified frequency
during normal operation. This clock signal should be a 3.3 V
LVTTL compatible signal. The processor provides a user-pro-
grammable 1
to 31
multiplication of the input clock to
support external-to-internal clock ratios. The MSEL6–0,
BYPASS, and DF pins decide the PLL multiplication factor at
reset. At run time, the multiplication factor can be controlled in
software. The combination of pull-up and pull-down resistors in
Figure 7 sets up a core clock ratio of 6:1, which, for example,
produces a 150 MHz core clock from the 25 MHz input. For
other clock multiplier settings, see the ADSP-BF535 Blackfin
Processor Hardware Reference.
All on-chip peripherals operate at the rate set by the system clock
(SCLK). The system clock frequency is programmable by means
of the SSEL pins. At run time the system clock frequency can be
controlled in software by writing to the SSEL fields in the PLL
control register (PLL_CTL). The values programmed into the
Power Dissipation Factor
fCCLKRED
fCCLKNOM
--------------------------
VDDINTRED
VDDINTNOM
------------------------------
2
×
=
fCCLKNOM
fCCLKRED
VDDINTNOM
VDDINTRED
Figure 7. Clock Ratio Example
CLKIN
CLKOUT
ADSP-BF535
MSEL5 (PF5)
MSEL4 (PF4)
MSEL3 (PF3)
MSEL2 (PF2)
MSEL1 (PF1)
MSEL0 (PF0)
RESET
MSEL6 (PF6)
DF (PF7)
VDD
BYPASS
RESET SOURCE
THE PULL-UP/PULL-DOWN
RESISTORS ON THE MSEL,
DF, AND BYPASS PINS SELECT
THE CORE CLOCK RATIO.
HERE, THE SELECTION (6:1)
AND 25MHz INPUT CLOCK
PRODUCE A 150MHz CORE CLOCK.
BLACKFIN PROCESSOR
VDD
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| ADSP-BF535PKBZ-350 | 功能描述:IC DSP CONTROLLER 16BIT 260-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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| ADSP-BF536BBC-4A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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