參數(shù)資料
型號: ADSP-BF535PKBZ-300
廠商: Analog Devices Inc
文件頁數(shù): 9/44頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 260 BGA
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: PCI,SPI,SSP,UART,USB
時(shí)鐘速率: 300MHz
非易失內(nèi)存: 外部
芯片上RAM: 308kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 260-BBGA
供應(yīng)商設(shè)備封裝: 260-PBGA(19x19)
包裝: 托盤
–17–
REV. A
ADSP-BF535
PIN DESCRIPTIONS
ADSP-BF535 Blackfin processor pin definitions are listed in
Table 7. The following pins are asynchronous: ARDY, PF15–0,
USB_CLK, NMI,
TRST, RESET, PCI_CLK, XTALI,
XTALO.
Table 7. Pin Descriptions
Pin
Type
Function
ADDR25 – 2
O/T
External address bus.
DATA31 – 0
I/O/T External data bus. (Pin has a logic-level hold circuit that prevents the input from floating
internally.)
ABE3–0/SDQM3–0
O/T
Asynchronous memory byte enables SDRAM data masks.
AMS3–0
O/T
Chip selects for asynchronous memories.
ARDY
1
I
Acknowledge signal for asynchronous memories.
AOE
O/T
Memory output enable for asynchronous memories.
ARE
O
Read enable for asynchronous memories.
AWE
O
Write enable for asynchronous memories.
CLKOUT/SCLK1
O
SDRAM clock output pin. Same frequency and timing as SCLK0. Provided to reduce
capacitance loading on SCLK0. Connect to SDRAM’s CK pin.
SCLK0
O
SDRAM clock output pin 0. Switches at system clock frequency. Connect to the
SDRAM’s CK pin.
SCKE
O/T
SDRAM clock enable pin. Connect to SDRAM’s CKE pin.
SA10
O/T
SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device
during host bus requests. Connect to SDRAM’s A10 pin.
SRAS
O/T
SDRAM row address strobe pin. Connect to SDRAM’s RAS pin.
SCAS
O/T
SDRAM column address select pin. Connect to SDRAM’s CAS pin.
SWE
O/T
SDRAM write enable pin. Connect to SDRAM’s WE or W buffer pin.
SMS3–0
O/T
Memory select pin of external memory bank configured for SDRAM. Connect to
SDRAM’s chip select pin.
TMR0
I/O/T Timer 0 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
TMR1
I/O/T Timer 1 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
TMR2
I/O/T Timer 2 pin. Functions as an output pin in PWMOUT mode and as an input pin in
WIDTH_CNT and EXT_CLK modes.
PF15/
SPI1SEL7
I/O/T Programmable flag pin. SPI output select pin.
PF14/
SPI0SEL7
I/O/T Programmable flag pin. SPI output select pin.
PF13/
SPI1SEL6
I/O/T Programmable flag pin. SPI output select pin.
PF12/
SPI0SEL6
I/O/T Programmable flag pin. SPI output select pin.
PF11/
SPI1SEL5
I/O/T Programmable flag pin. SPI output select pin.
PF10/
SPI0SEL5
I/O/T Programmable flag pin. SPI output select pin (used during SPI boot).
PF9/
SPI1SEL4/SSEL1
I/O
Programmable flag pin. SPI output select pin. Sampled during reset to determine core
clock to system clock ratio.
PF8/
SPI0SEL4/SSEL0
I/O
Programmable flag pin. SPI output select pin. Sampled during reset to determine core
clock to system clock ratio.
PF7/
SPI1SEL3/DF
I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. DF = 1 is for high frequency clock and divides
the input clock by 2. DF = 0 passes input clock directly to PLL phase detector.
PF6/
SPI0SEL3/MSEL6 I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
PF5/
SPI1SEL2/MSEL5 I/O
Programmable flag pin. SPI output select pin. Sensed for configuration state during
hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.
Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state
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