- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19503 > ADSP-BF535PKBZ-300 (Analog Devices Inc)IC DSP CONTROLLER 16BIT 260 BGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-BF535PKBZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 260 BGA |
| 產(chǎn)品培訓(xùn)模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | PCI，SPI，SSP，UART，USB |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 308kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 260-BBGA |
| 供應(yīng)商設(shè)備封裝： | 260-PBGA（19x19） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
–37–
REV. A
ADSP-BF535
The frequency f includes driving the load high and then back low.
For example: DATA31–0 pins can drive high and low at a
maximum rate of 1/(2
tSCLK) while in SDRAM burst mode.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Note that the conditions causing a worst-case PEXT differ from
those causing a worst-case P
INT . Maximum PINT cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an appli-
cation to have 100% or even 50% of the outputs switching
simultaneously.
Test Conditions
All timing parameters appearing in this data sheet were measured
under the conditions described in this section.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from the
point when a reference signal reaches a high or low voltage level
to the point when the output starts driving as shown in the Output
the interval from when the reference signal switches to when the
output voltage reaches 2.0 V (output high) or 1.0 V (output low).
Time tTRIP is the interval from when the output starts driving to
when the output reaches the 1.0 V or 2.0 V trip voltage. Time
tENA is calculated as shown in the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L and the
load current, IL. This decay time can be approximated by the
equation:
The output disable time tDIS is the difference between
tDIS_MEASURED is the interval from when the reference signal
switches to when the output voltage decays
V from the measured
output high or output low voltage. The time tDECAY is calculated
with test loads CL and IL, and with
V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
V
to be the difference between the ADSP-BF535 Blackfin proces-
sor’s output voltage and the input threshold for the device
requiring the hold time. A typical
V will be 0.4 V. C
L is the total
bus capacitance (per data line), and IL is the total leakage or three-
state current (per data line). The hold time will be tDECAY plus the
minimum disable time (for example, tDSDAT for an SDRAM write
cycle).
Table 27. PLL Power Dissipation
Parameter
Test Conditions
Typical
Unit
IDDPLL
VDDPLL=1.5 V, 25C
4.0
mA
PTOTAL
PEXT
I
( DD VDDINT
×)
+
=
tENA tENA_MEASURED
=
tTRIP
–
tDECAY
CLV
() IL
=
Figure 22. Output Enable/Disable
Figure 23. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 24. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
VOH (MEASURED)
V
VOL (MEASURED) + V
tDIS_MEASURED
VOH
(MEASURED)
VOL
(MEASURED)
2.0V
1.0V
VOH
(MEASURED)
VOL
(MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS DRIVING
tENA
tDECAY
tENA-MEASURED
tTRIP
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GCM15DCTN-S288 | CONN EDGECARD 30POS .156 EXTEND |
| V300A36E400BL3 | CONVERTER MOD DC/DC 36V 400W |
| KRM55WR71H226MH01K | CAP CER 22UF 50V 20% X7R 2220 |
| VE-B10-CX-B1 | CONVERTER MOD DC/DC 5V 75W |
| MLP2012S1R5M | INDUCTOR MULTILAYER 1.5UH 0805 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF535PKBZ-350 | 功能描述:IC DSP CONTROLLER 16BIT 260-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF536BBC-3A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF536BBC-4A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF536BBCZ-3A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF536BBCZ-3AX | 制造商:Analog Devices 功能描述:182-MBGA PB-FREE - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。