參數(shù)資料
型號(hào)： ADSP-BF535PKBZ-300
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/44頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 260 BGA
產(chǎn)品培訓(xùn)模塊： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： PCI，SPI，SSP，UART，USB
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 308kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.50V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 260-BBGA
供應(yīng)商設(shè)備封裝： 260-PBGA（19x19）
包裝： 托盤
ADSP-BF535
–12–
REV. A
(BYPASS) in the PLL Control register (PLL_CTL). If bypass is
disabled, the processor transitions to the full on mode. If bypass
is enabled, the processor transitions to the Active mode.
When in Sleep mode, system DMA access to L1 memory is not
supported.
Deep Sleep Operating Mode
– Maximum Power Savings
The deep sleep mode maximizes power savings by disabling the
clocks to the processor core (CCLK) and to all synchronous
peripherals (SCLK). Asynchronous peripherals, such as the
RTC, may still be running but will not be able to access internal
resources or external memory. This powered down mode can
only be exited by assertion of the reset interrupt (
RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, assertion of
RESET causes the processor to sense
the value of the BYPASS pin. If bypass is disabled, the processor
will transition to full on mode. If bypass is enabled, the processor
will transition to active mode. When in deep sleep mode,
assertion of the RTC asynchronous interrupt causes the
processor to transition to the full on mode, regardless of the value
of the BYPASS pin.
The DEEPSLEEP output is asserted in this mode.
Mode Transitions
The available mode transitions diagrammed in Figure 6 are
accomplished either by the interrupt events described in the
following sections or by programming the PLLCTL register with
the appropriate values and then executing the PLL programming
sequence.
This instruction sequence takes the processor to a known idle
state with the interrupts disabled. Note that all DMA activity
should be disabled during mode transitions.
Power Savings
As shown in Table 4, the ADSP-BF535 Blackfin processor
supports five different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance
with industry standards and conventions. By isolating the internal
logic of the ADSP-BF535 Blackfin processor into its own power
domain, separate from the PLL, RTC, PCI, and other I/O, the
processor can take advantage of dynamic power management,
without affecting the PLL, RTC, or other I/O devices.
Table 3. Operating Mode Power Settings
Mode
PLL
Bypassed
Core Clock
(CCLK)
System Clock
(SCLK)
Full On
Enabled No
Enabled
Active
Enabled Yes
Enabled
Sleep
Enabled Yes or No Disabled
Enabled
Deep +
Disabled
Figure 6. Mode Transitions
STOPCK = 1
AND PDWN = 0
WAKEUP AND
BYPASS = 1
WAKEUP AND
BYPASS = 0
SLEEP
STOPCK = 1
AND PDWN = 0
FULL-ON
ACTIVE
PDWN = 1
BYPASS = 1
ANDSTOPCK= 0
AND PDWN = 0
RTC_WAKEUP
DEEP
SLEEP
HARDWARE
RESET
MSEL = NEW
AND PLL_OFF = 0
AND BYPASS = 1
MSEL = NEW
AND PLL_OFF = 0
AND BYPASS = 0
BYPASS = 0
AND PLL_OFF = 0
AND STOPCK = 0
AND PDWN = 0
Table 4. Power Domains
Power Domain
VDD Range
All internal logic, except PLL and RTC
VDDINT
Analog PLL internal logic
VDDPLL
RTC internal logic and crystal I/O
VDDRTC
PCI I/O
VDDPCIEXT
All other I/O
VDDEXT
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