參數(shù)資料
型號(hào)： ADV7183ABST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 11/104頁(yè)
文件大小： 894K
代理商： ADV7183ABST
ADV7183A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 11 of 104
F
80
O
79
N
78
N
77
P
76
P
75
P
74
P
73
D
72
D
71
N
70
N
69
S
68
S
67
A
66
N
65
R
64
N
63
A
62
A
61
VS
HS
1
2
DGND
DVDDIO
3
4
P11
P10
P9
P8
5
6
7
8
DGND
DVDD
10
NC
11
SFL
12
NC
13
DGND
14
DVDDIO
15
NC
16
NC
17
NC
18
P7
19
P6
20
9
AIN5
AIN11
AIN4
AIN10
AGND
CAP C2
CAP C1
AGND
CML
REFOUT
AVDD
CAP Y2
CAP Y1
AGND
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P
21
P
22
P
23
P
24
N
25
L
26
L
27
X
28
X
29
D
30
D
31
P
32
P
33
N
34
N
35
P
36
E
37
P
38
A
39
A
40
ADV7183A
TOP VIEW
(Not to Scale)
NC = NO CONNECT
0
Figure 5. 80-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
3, 9, 14, 31, 71
39, 40, 47, 53, 56
4, 15
10, 30, 72
50
38
41–46, 57–62
11, 13, 16–18, 25,
34, 35, 63, 65, 69,
70, 77, 78
5–8, 19–24,
32, 33, 73–76
2
1
80
67
68
66
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1–AIN12
NC
Type
G
G
P
P
P
P
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
P0–P15
O
Video Pixel Output Port.
HS
VS
FIELD
SDA
SCLK
ALSB
O
O
O
I/O
I
I
HS is a horizontal synchronization output signal.
VS is a vertical synchronization output signal.
FIELD is a field synchronization output signal.
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input (Max Clock Rate of 400 kHz).
This pin selects the I
2
C address for the ADV7183A. ALSB set to Logic 0 sets the address for a
write as 0x40; for ALSB set to logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7183A circuitry.
This is a line-locked output clock for the pixel data output by the ADV7183A. Nominally
27 MHz, but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the
ADV7183A. Nominally 13.5 MHz, but varies up or down according to video line length.
64
RESET
I
27
LLC1
O
26
LLC2
O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7183AKST 制造商:Analog Devices 功能描述:MULTIFORMAT SDTV VIDEO DECODER 制造商:Rochester Electronics LLC 功能描述:10BIT NTSC/PAL/SECAMVIDDECOD I.C - Tape and Reel 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7183AKST-U1 制造商:Analog Devices 功能描述:VID DECODER 80LQFP - Bulk
ADV7183AKST-X2 制造商:Analog Devices 功能描述:VID DECODER - Bulk
ADV7183AXST 制造商:Analog Devices 功能描述:VIDEO DECODER I.C. - Bulk
ADV7183AXST-X2 制造商:Analog Devices 功能描述:VIDEO DECODER I.C. - Bulk
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