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參數(shù)資料
| 型號(hào)： | ADV7330KST |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁(yè)數(shù)： | 52/76頁(yè) |
| 文件大小： | 1378K |
| 代理商： | ADV7330KST |
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REV. B
–52–
ADV7330
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7330
should be avoided to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the analog
power plane.
Analog Signal Interconnect
The ADV7330 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure 52. The
termination resistors should be as close as possible to the
ADV7330 to minimize reflections.
For optimum performance, it is recommended that all decoupling
and external components relating to ADV7330 be located on the
same side of the PCB and as close as possible to the ADV7330.
Any unused inputs should be tied to ground.
5k
V
DD_IO
5k
V
DD_IO
COMP
36
V
AA
41
V
DD
V
DD_IO
1
ADV7330
I
2
C
19
HSYNC_O/P
50
VSYNC_O/P
49
BLANK_O/P
48
HSYNC_I/P
23
VSYNC_I/P
24
BLANK_I/P
25
RESET
33
CLKIN
32
EXT_LF
34
UNUSED
INPUTS
SHOULD BE
GROUNDED
C0–C7
Y0–Y7
V
AA
4.7 F
+
4.7k
820pF
3.9nF
V
AA
GND_ IO
64
AGND
40
DGND
2, 11, 14, 15,
51–55, 57–63
I
2
C BUS
10nF
0.1 F
10nF
0.1 F
10, 56
V
DD_IO
V
DD
10nF
1 F
V
AA
+
0.1 F
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
V
AA
V
DD_IO
DAC A
39
300
CVBS/GREEN/Y
DAC B
38
300
LUMA/BLUE/Pb
DAC C
37
300
CHROMA/RED/Pr
V
REF
46
100nF
1.1k
V
AA
RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE
SCLK
22
100
SDA
21
ALSB
20
R
SET
35
3040
SELECTION HERE
DETERMINES
DEVICE ADDRESS
5k
V
DD_IO
680
5k
100
Figure 52. ADV7330 Circuit Layout
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