2-44 Revision 17 Table 2-71 Parameter Definition and Measuring Nodes Parameter Name Parameter " />
參數(shù)資料
型號(hào): AGLN250V5-CSG81I
廠商: Microsemi SoC
文件頁數(shù): 108/150頁
文件大小: 0K
描述: IC FPGA NANO 1KB 250K 81-CSP
標(biāo)準(zhǔn)包裝: 640
系列: IGLOO nano
邏輯元件/單元數(shù): 6144
RAM 位總計(jì): 36864
輸入/輸出數(shù): 60
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-WFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 81-CSP(5x5)
IGLOO nano DC and Switching Characteristics
2-44
Revision 17
Table 2-71 Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
Measuring Nodes
(from, to)*
tOCLKQ
Clock-to-Q of the Output Data Register
HH, DOUT
tOSUD
Data Setup Time for the Output Data Register
FF, HH
tOHD
Data Hold Time for the Output Data Register
FF, HH
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
LL, DOUT
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
LL, HH
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
LL, HH
tOECLKQ
Clock-to-Q of the Output Enable Register
HH, EOUT
tOESUD
Data Setup Time for the Output Enable Register
JJ, HH
tOEHD
Data Hold Time for the Output Enable Register
JJ, HH
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
II, EOUT
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
II, HH
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
II, HH
tICLKQ
Clock-to-Q of the Input Data Register
AA, EE
tISUD
Data Setup Time for the Input Data Register
CC, AA
tIHD
Data Hold Time for the Input Data Register
CC, AA
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
DD, EE
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
DD, AA
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
DD, AA
Note: *See Figure 2-13 on page 2-43 for more information.
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