2-46 Revision 17 1.2 V DC Core Voltage Table 2-73 Input Data Register Propagation Delay" />
參數(shù)資料
型號: AGLN250V5-CSG81I
廠商: Microsemi SoC
文件頁數(shù): 110/150頁
文件大?。?/td> 0K
描述: IC FPGA NANO 1KB 250K 81-CSP
標準包裝: 640
系列: IGLOO nano
邏輯元件/單元數(shù): 6144
RAM 位總計: 36864
輸入/輸出數(shù): 60
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-WFBGA,CSBGA
供應商設備封裝: 81-CSP(5x5)
IGLOO nano DC and Switching Characteristics
2-46
Revision 17
1.2 V DC Core Voltage
Table 2-73 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tICLKQ
Clock-to-Q of the Input Data Register
0.68
ns
tISUD
Data Setup Time for the Input Data Register
0.97
ns
tIHD
Data Hold Time for the Input Data Register
0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
1.19
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
1.19
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.24
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.24
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.19
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.19
ns
tICKMPWH
Clock Minimum Pulse Width HIGH for the Input Data Register
0.31
ns
tICKMPWL
Clock Minimum Pulse Width LOW for the Input Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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