參數(shù)資料
型號(hào)： AM29N323DT11AWKI
廠商： Advanced Micro Devices, Inc.
英文描述： 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 32兆位（2米× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫(xiě)，突發(fā)模式閃存
文件頁(yè)數(shù)： 12/48頁(yè)
文件大?。?/td> 824K
代理商： AM29N323DT11AWKI
August 8, 2002
Am29N323D
11
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through V
PP
. This function is primarily intended to
allow faster manufacturing throughput at the factory. If
the system asserts V
ID
on this input, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the input to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
ID
from the V
PP
input returns the device to normal
operation.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Functions and Au-
toselect Command Sequence sections for more
information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at V
CC
± 0.2 V.
The device requires standard access time (t
CE
) for
read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
60 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC4
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of re-
setting the device to reading array data. When
RESET# is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all outputs, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.2 V, the device
draws CMOS standby current (I
CC4
). If RESET# is
held at V
IL
but not within V
SS
±0.2 V, the standby cur-
rent will be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory. Note that RESET# must be as-
serted low during device power-up for proper
operation.
If RESET# is asserted during a program or erase op-
eration, the device requires a time of t
READY
(during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a pro-
gram or erase operation is not executing, the reset
operation is completed within a time of t
READY
(not
during Embedded Algorithms). The system can read
data t
RH
after RESET# returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to
Figure 11
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device
is disabled. The outputs are placed in the high
impedance state.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to
Table 4
for com-
mand definitions).
The device offers three types of data protection at the
sector level:
■
The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.
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