參數(shù)資料
型號： AM29N323DT11AWKI
廠商： Advanced Micro Devices, Inc.
英文描述： 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 32兆位（2米× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存
文件頁數(shù)： 16/48頁
文件大?。?/td> 824K
代理商： AM29N323DT11AWKI
August 8, 2002
Am29N323D
15
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations.
Table 4
defines the valid register command
sequences. Writing
incorrect
address and data
values
or writing them in the
improper sequence
resets the device to reading array data.
All addresses are latched on the rising edge of AVD#.
All data is latched on the rising edge of WE#. Refer to
the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read data
from any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the
Erase Suspend/Erase Resume Commands section for
more information.
The system
must
issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.
See also Requirements for Asynchronous
Read Operation (Non-Burst) and Requirements for
Synchronous (Burst) Read Operation in the Device
Bus Operations section for more information. The
Asynchronous Read and Synchronous/Burst Read
tables provide the read parameters, and Figures
9
and
10
show the timings.
Set Wait State Command Sequence
The wait state command sequence instructs the device
to set a particular number of clock cycles for the initial
access in burst mode. The number of wait states that
should be programmed into the device is directly
related to the clock frequency. The first two cycles of
the command sequence are for unlock purposes. On
the third cycle, the system should write C0h to the
address associated with the intended wait state setting
(see
Table 3
). Address bits A12 and A13 determine the
setting.
Table 3.
Third Cycle Address/Data
Upon power up, the device defaults to the maximum
seven cycle wait state setting (see
Figure 20
). It is rec-
ommended that the wait state command sequence be
written, even if the default wait state value is desired, to
ensure the device is set as expected. A hardware reset
will set the wait state to the default setting.
Enable PS (Power Saving) Mode
Command Sequence
The Enable PS (Power Saving) Mode command
sequence is required to set the device to the PS mode.
On power up, the Power Saving mode is disabled. The
command sequence consists of two unlock cycles fol-
lowed by a command cycle in which the address and
data should 555h/70h, respectively. The PS mode
remains enabled until the device is hardware reset
(either device is powered down or RESET# is asserted
low).
Sector Lock/Unlock Command Sequence
The sector lock/unlock command sequence allows the
system to determine which sectors are protected from
accidental writes. When the device is first powered up,
all sectors are locked. To unlock a sector, the system
must write the sector lock/unlock command sequence.
Two cycles are first written: addresses are don’t care
and data is 60h. During the third cycle, the sector
address (SLA) and unlock command (60h) is written,
while specifying with address A6 whether that sector
should be locked (A6 = V
IL
) or unlocked (A6 = V
IH
).
After the third cycle, the system can continue to lock or
unlock additional cycles, or exit the sequence by
writing F0h (reset command).
Note that the last two outermost boot sectors can be
locked by taking the WP# signal to V
IL
. Also, if V
PP
is
at V
IL
all sectors are locked; if the V
PP
input is at V
PP
,
all sectors are unlocked.
Reset Command
Writing the reset command resets the banks to the read
or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which
Address
Total Wait State Cycles
Data
000555h
4
C0h
001555h
5
002555h
6
003555h
7
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